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參數(shù)資料
| 型號(hào)： | 5962R0150201VYC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 29/55頁 |
| 文件大小： | 685K |
| 代理商： | 5962R0150201VYC |
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35
significant word. All register pairs may be the source or
destination operands.
Special Purpose Data Registers
In addition to the 20 general purpose data registers, the
UT1750AR has three special purpose data registers: (1) The
ACCUMULATOR (ACC); (2) the Stack Pointer (SP); and (3)
the Instruction Counter Save Register (ICS).
The Accumulator (ACC) is a 32-bit register used only with
multiply, divide, extended shift, Load Register from Instruction
memory (LRI), and Store Register to Instruction memory
(STRI) instructions. For multiply instructions, the ACC retains
the most significant half of the product, and for divide
instructions, the ACC retains the remainder. For LRI and STRI
instructions, the ACC contains the instruction memory pointer.
Note that the ACC can be used as a general purpose register for
most operations.
The Stack Pointer (SP) is a 16-bit register usable only with POP
and PUSH instructions.
The Instruction Counter Save (ICS) register is a 20-bit register
used during calls, jumps, and interrupts.
Register Notation
The UT1750AR’s RISC instruction descriptions contain a
definition of the Register Transfer Language (RTL) that the
RISC Assembler uses to describe how the RISC instructions
operate. The RTL description of the UT1750AR’s internal
registers is as follows:
RSn
-- Source Register where n specifies the register
number.
RDn
-- Destination Register where n specifies the
register number.
XRSn -- Long-Data Source Register where n
specifies the register number.
XRDn -- Long-Data Destination Register where n
specifies the register number.
IC
-- Instruction Counter
SP
-- Stack Pointer
ACC -- 32-bit Accumulator
ICS
-- Instruction Counter Store Register
@RSn -- Data Register Indirect where n specifies the
register number
@SP -- Stack Pointer Indirect
#
-- Immediate Data
@#
-- Immediate Data Indirect
Instruction Formats
The UT1750AR has three instruction formats (figure 32): (1)
Register-to-Register; (2) Register-to-Short Immediate; and (3)
Register-to-Immediate.
All the UT1750AR’s instructions are either word (16-bit) or
long-word (32-bit) in length. The only time the UT1750AR uses
the long-word instruction format is for the Immediate Source
Operand Address Mode.
0
4
5
9
10
14
15
Figure 32b. RegisterX 106to-Short Immediate
0
4
5
9
10
14
15
Figure 32a. RegisterX0106to-Register Instruction Format
Figure 32c. Register Immediate Instruction Format
MSB
LSB
MODE
OPCODE
DESTINATION
SOURCE
0
XXXXX
RD
RS
MODE
OPCODE
DESTINATION
SOURCE
MSB
LSB
1
XXXXX
RD
IMMEDIATE
MODE
MSB
OPCODE
DESTINATION
SOURCE
LSB
0
XXXXX
RD
11111
0
4
5
9
10
14
15
16-Bit Immediate Data
15
0
MSB
LSB
Instruction Format
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