參數(shù)資料
型號(hào)： 5962R0150201VYC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144
封裝： CERAMIC, PGA-144
文件頁數(shù)： 2/55頁
文件大?。?/td> 685K
代理商： 5962R0150201VYC
10
RA16/OD3
38
P9
TTO
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
RD0
RISC Instruction Address Bus/Output Discretes. When the
UT1750AR is operating in the RISC mode (M1750 = 0)
these four bits represent the four most significant address
bits. In the MIL- STD-1750A mode (M1750 = 1) these four
bits are user-programmable output discretes defined as
follows:
RA19/ CS = Chip Select (AL)
RA18/OD1 = Output Discrete 1
RA17/OD2 = Output Discrete 2
RA16/OD3 = Output Discrete 3
These output discretes are programmed with the Output
Register (OTR) RISC opcode. These signals enter a high-
impedance state when the UT1750AR is in the test mode
(TEST = 0).
130
H1
TTB
--
RISC Instruction Data Bus. This bidirectional data bus is
the interface with the RISC memory. When the
UT1750AR is in the MIL-STD-1750A mode of
operation, the data comes from the emulation ROMs.
This data is executed to emulate the MIL-STD-1750A
Instruction Set. RD15 is the most significant bit. The
RISC Data Bus enters a high-impedance state only when
the UT1750AR is in the test mode (TEST = 0).
V
34
H3
+5 VDC Power. Power supply input.
--
RISC BUSSES
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
RA17/OD2
Continued from page 9.
RA18/OD1
RA19/CS
39
40
41
P10
N10
R11
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD8
RD9
RD10
RD11
RD12
RD13
RD14
RD15
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
J1
K1
J2
K2
K3
L1
M1
N1
M2
L3
N2
P1
M3
N3
P2
67
100
132
N9
G13
C7
J3
N8
H13
C8
POWER AND GROUND
V
1
33
66
99
Reference Ground. Zero VDC logic ground.
--
DD
SS
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