- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄293971 > 5962R0150201VYC 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 PDF資料下載
參數(shù)資料
| 型號： | 5962R0150201VYC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 30/55頁 |
| 文件大?。?/td> | 685K |
| 代理商： | 5962R0150201VYC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
36
The bits in the RISC instructions are defined as follows:
M: Instruction Mode Bit. When M = 1, the UT1750AR
interprets the Instruction Source field as a five-bit literal
value. If M = 0, the UT1750AR uses the Instruction Source
field to specify the source register for the instruction.
Opcode: This field is the five-bit opcode the UT1750AR
uses to decode the RISC instruction into a machine
operation.
Destination: This field specifies the register the UT1750AR
uses for the destination of the instruction.
Source: This field specifies the register the UT1750AR uses
for the Instruction Source.
Immediate: If needed, this field contains the 16-bits of
immediate data the UT1750AR requires for the long-
immediate instruction.
Operand Addressing Modes
The UT1750AR’s RISC instruction set supports four basic
addressing modes. All RISC instructions require a source
operand and a destination operand. The destination operand is
a data register (RDn or XRDn) for all RISC instructions, except
the Jump on Condition (JC) instruction where the destination
register contains a template for the jump condition tested for in
the instruction. The source operand can be either a data register
or immediate data for all RISC instructions.
The source operand can also be addressed in an indirect mode.
In an indirect addressing mode, the source data register or the
Stack Pointer contains an effective address. This address points
to the memory location for operand data the UT1750AR uses
during the current instruction execution. This type of memory
addressing is only used with the Load (LR), Store (STR), PUSH,
and POP RISC instructions.
Destination Addressing Mode
The destination operand is given explicitly for all UT1750AR
RISC instructions. The UT1750AR encodes a five-bit field, bits
9 through 5, in each instruction as follows:
R0 -- 00000
XR0 -- 10000
R1 -- 00001
R16 -- 10001
R2 -- 00010
XR2 -- 10010
R3 -- 00011
R17 -- 10011
R4 -- 00100
XR4 -- 10100
R5 -- 00101
XR16 -- 10110
R6 -- 10110
R7 -- 00111
XR8 -- 11000
R8 -- 01000
R18 -- 11001
R10 -- 01010
XR10 -- 11010
R11 -- 01011
R19 -- 11011
R12 -- 01100
XR12 -- 11100
R13 -- 01101
XR18 -- 11101
R14 -- 01110
XR14 -- 11110
R15 -- 01111
ACC -- 11111
NUL -- 10111
In 1750 emulation mode register pairs XR8, XR10 and XR12
have a special meaning. Register XR8 is a pointer to the MIL-
STD-1750A destination register (defined as RA). Register pair
XR10 is a pointer to the next register, RA+1. Register pair XR12
is a pointer to the source register.
Source Addressing Modes
The UT1750AR directly addresses the source operand by using
one of three normal modes: (1) Data Register Direct; (2) Literal;
and (3) Immediate Long Data.
Data Register Direct
When the UT1750AR uses the Data Register Direct mode, the
source operand is one of the data registers. The data register is
explicitly stated for all RISC instructions. The UT1750AR
encodes a 5-bit field, bits 4 through 0, in each instruction as
follows:
R0 -- 00000
XR0 -- 10000
R1 -- 00001
R16 -- 10001
R2 -- 00010
XR2 -- 10010
R3 -- 00011
R17 -- 10011
R4 -- 00100
XR4 -- 10100
R5 -- 00101
XR16 -- 10101
R6 -- 00110
XR6 -- 10110
R7 -- 00111
R8 -- 01000
XR8 -- 11000
R9 -- 01001
R18 -- 11001
R10 -- 01010
XR10 -- 11010
R11 -- 01011
R19 -- 11011
R12 -- 01100
XR12 -- 11100
R13 -- 01101
XR18 -- 11101
R14 -- 01110
XR14 -- 11110
R15 -- 01111
Reserved -- 10111
and 11111
In 1750 emulation mode register pairs XR8, XR10 and XR12
have a special meaning. Register XR8 is a pointer to the MIL-
STD-1750A destination register (defined as RA). Register pair
XR10 is a pointer to the next register, RA+1. Register pair XR12
is a pointer to the source register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962R0150202VYX | 16-BIT, 16 MHz, RISC PROCESSOR, QFP132 |
| 5962R0722402VYC | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 5962R8958702VXA | 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16 |
| 5962R9215311VTA | 32K X 8 STANDARD SRAM, 55 ns, CDFP36 |
| 5962R9215311VTX | 32K X 8 STANDARD SRAM, 55 ns, CDFP36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962R0253801VZA | 制造商:Analog Devices 功能描述:- Rail/Tube |
| 5962R0720802VXC | 制造商:Texas Instruments 功能描述:ADS5463 RHA QMLV DEVICE |
| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
| 5962R0722701VZA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
發(fā)布緊急采購，3分鐘左右您將得到回復。