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參數(shù)資料
| 型號： | 5962R0150201VYC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 34/55頁 |
| 文件大?。?/td> | 685K |
| 代理商： | 5962R0150201VYC |
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4
FUNCTIONAL PINOUT
Legend for TYPE and ACTIVE fields:
TO
= TTL output
TI
= TTL input
TUI
= TTL input (pull-up)
TDI
= TTL input (pull-down)
TTO
= Three-state TTL output
TTB
= Three-state TTL bidirectional
CO
= CMOS output
OSC
= Oscillator input to a Pierce Oscillator inverter
AH
= Active High
AL
= Active Low
OSCIN
50
P14
OSC
OSCILLATOR AND CLOCK SIGNALS
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
OSCOUT
SYSCLK
51
52
P15
M14
CO
TO
Oscillator Input. A 50% duty cycle crystal-drive input for
driving the UT1750AR.
Oscillator Output. A 50% duty cycle, single-phase clock
output at the same frequency as the OSCIN input.
System Output. The buffered equivalent of the OSCOUT
signal.
NUI1
129
H2
TI
PROCESSOR STATUS
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
NUI2
NUO3
44
126
P12
G3
TUI
TTO
Not used input 1. Internal UTMC use only. Tie either high
or low.
Not used input 2. Internal UTMC use only. Tie low.
Not used output 3. Internal UTMC use only. NUO3 enter
high impedance state when the UT1750AR is in the test
mode (TEST=0)
--
M1750
45
N11
TDI
AH
STATE1
Mode Select RISC/1750. A high on M1750 places the
UT1750AR into the MIL-STD-1750A emulation mode.
A low on M1750 places the UT1750AR into the RISC
mode. It is tied to an internal pull-down resistor.
54
N15
TTO
Processor State. This signal indicates the internal state of
the UT1750AR. A low on STATE1 indicates the
UT1750AR is executing a new RISC instruction. A high
on STATE1 indicates the UT1750AR is fetching a RISC
instruction. STATE1 enters a high-impedance state when
the UT1750AR is in the test mode ( TEST=0).
--
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