參數(shù)資料
型號(hào)： 403GC-3BA25C1
元件分類： 復(fù)位半導(dǎo)體
英文描述： 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述： 32位微處理器
文件頁(yè)數(shù)： 6/48頁(yè)
文件大小： 768K
代理商： 403GC-3BA25C1
IBM PowerPC 403GC
6
The programmable interval timer is a 32-bit
register that is decremented at the same rate as
the time base is incremented. The user preloads
the PIT register with a value to create the desired
delay. When the register is decremented to
zeros, the timer stops decrementing, a bit is set
in the timer status register (TSR), and a PIT
interrupt is generated. Optionally, the PIT can be
programmed to reload automatically the last
value written to the PIT register, after which the
PIT begins decrementing again.The timer control
register (TCR) contains the interrupt enable for
the PIT interrupt.
The fixed interval timer generates periodic
interrupts based on selected bits in the time
base. Users may select one of four intervals for
the timer period by setting the correct bits in the
TCR. When the selected bit in the time base
changes from 0 to 1, a bit is set in the TSR and a
FIT interrupt is generated. The FIT interrupt
enable is contained in the TCR.
The watchdog timer generates a periodic
interrupt based on selected bits in the time base.
Users may select one of four time periods for the
interval and the type of reset generated if the
watchdog timer expires twice without an
intervening clear from software. If enabled, the
watchdog timer generates a system reset unless
an exception handler updates the watchdog timer
status bit before the timer has completed two of
the selected timer intervals.
Serial Port
The 403GC serial port is capable of supporting
RS232 standard serial communication, as well as
high-speed execution (bit speed at a maximum of
one-sixteenth of the SysClk processor clock
rate). The serial clock which drives the serial port
can come from the internal SysClk or an external
clock source at the external serial clock pin
(maximum of one-half the SysClk rate).
The 403GC serial port contains many features
found only on advanced communications
controllers, including the capability of being a
peripheral for DMA transfers. An internal
loopback mode supports diagnostic testing
without requiring external hardware. An auto
echo mode is included to retransmit received bits
to the external device. Auto-resynchronization
after a line break and false start bit detection are
also provided, as well as operating modes that
allow the serial port to react to handshaking line
inputs or control handshaking line outputs
without software interaction. Program generation
mode allows the serial port transmitter to be used
for pulse width modulation with duty cycle
variation controlled by frame size, baud rate, and
data pattern.
JTAG Port
The JTAG port has been enhanced to allow it to
be used as a debug port. Through the JTAG test
access port, debug software on a workstation or
PC can single-step the processor and interrogate
internal processor state to facilitate software
debugging. The standard JTAG boundary-scan
register allows testing of circuitry external to the
chip, primarily the board interconnect.
Alternatively, the JTAG bypass register can be
selected when no other test data register needs
to be accessed during a board-level test
operation.
Real-Time Debug Port
The real-time debug port supports tracing the
instruction stream being executed out of the
instruction cache in real time. The trace status
signals provide trace information while in real-
time trace debug mode. This mode does not alter
the performance of the processor.
P/N Code
Notes:
1. The dash number indicates the speed version.
2. The characters in the dash number indicate
reliability grade, package type (J or B), revision level
(A), and commercial version (C), and the ratio of
internal CPU core clock rate to external bus speed.
3. PQFP and PBGA versions are both reliability grade
3, but only the PBGA part numbers specify the grade.
Table 3. PPC403GC Part Numbers
MHz
Part Number
Package
25
PPC403GC-JA25C1
403GC-3BA25C1
PQFP
PBGA
33
PPC403GC-JA33C1
403GC-3BA33C1
PQFP
PBGA
40
PPC403GC-JA40C1
403GC-3BA40C1
PQFP
PBGA
相關(guān)PDF資料
PDF描述
403GC-3BA33C1 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GC-3BA40C1 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GCX-3BC50C2 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GCX-3BC66C2 32-Bit Microprocessor
403GCX-3BC80C2 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
403GC-3BA33C1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GC-3BA40C1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GCX2JC66C2 制造商:IBM 功能描述:38R2233
403GCX-3BC50C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GCX-3BC66C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
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