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參數(shù)資料
| 型號： | 403GC-3BA25C1 |
| 元件分類： | 復位半導體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 3/48頁 |
| 文件大小： | 768K |
| 代理商： | 403GC-3BA25C1 |
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IBM PowerPC 403GC
3
Control functions for direct-connect I/O devices
and for DRAM, SRAM, or ROM banks are
provided by the BIU. Burst access for SRAM,
ROM, and page-mode DRAM devices is
supported for cache fill and flush operations.
The BIU controls the transfer of data between the
external bus and the instruction cache, the data
cache, or registers internal to the processor core.
The BIU also arbitrates among external bus
master and DMA transfers, the internal buses to
the cache units and the register banks, and the
serial port on the on-chip peripheral bus (OPB).
Memory Addressing Regions
The 403GC can address an effective range of
four gigabytes, mapped to 3.5GB (256MB for
SRAM/ROM or other I/O, 256MB DRAM, and
3GB OPB/reserved) of physical address space
containing twenty-eight 128MB regions.
Cacheability with respect to the instruction or
data cache is programmed via the instruction and
data cache control registers, respectively.
Within the DRAM and SRAM/ROM regions, a
total of eight banks of devices are supported.
Each bank can be configured for 8-, 16-, or 32-bit
devices.
For individual DRAM banks, the number of wait
states, bank size,
RAS
-to-
CAS
timing, use of an
external address multiplexer (for external bus
masters), and refresh rate are user-
programmable. For each SRAM/ROM bank, the
bank size, bank location, number of wait states,
and timings of chip selects, byte enables, and
output enables are all user-programmable.
Memory Management Unit
The memory management unit (MMU) supports
address translation and protection functions for
embedded applications. When used with
appropriate system level software, the MMU
provides the following functions: translation of
4GB logical address space into physical
addresses, independent enabling of instruction
and data translation/protection, page level
cacheability and access control via the
translation mechanism, software control of page
replacement strategy, and additional control over
protection via zones.
The fully associative 64-entry TLB array handles
both instruction and data accesses. The
translation for any virtual address can be placed
in any one of the 64 entries, allowing maximum
flexibility by TLB management software. Each
TLB entry contains a translation for a page that
can be any one of eight sizes from 1KB to 16MB,
incrementing by powers of 4.
The TLB can simultaneously contain any mix of
page sizes. This feature enables the use of small
pages when maximum granularity is required,
reducing the amount of wasted memory when
compared to the more common fixed 4KB page
size.
Table 1. 403GC Instructions by Category
Category
Base Instructions
Data Movement
Arithmetic / Logical
load, store
add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign
extension, count leading zeros
compare, compare logical, compare immediate
branch, branch conditional
condition register logical
rotate, rotate and mask, shift left, shift right
invalidate, touch, zero, flush, store
write to external interrupt enable bit, move to/from machine state register,
return from interrupt, return from critical interrupt
system call, synchronize, move to/from device control registers, move to/
from special purpose registers
Comparison
Branch
Condition
Rotate/Shift
Cache Control
Interrupt Control
Processor Management
相關PDF資料 |
PDF描述 |
|---|---|
| 403GC-3BA33C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GC-3BA40C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC50C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC66C2 | 32-Bit Microprocessor |
| 403GCX-3BC80C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 403GC-3BA33C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GC-3BA40C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
| 403GCX-3BC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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