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參數(shù)資料
| 型號： | 403GC-3BA25C1 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大小： | 768K |
| 代理商： | 403GC-3BA25C1 |
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IBM PowerPC 403GC
27
Notes:
1. For normal RAS and CAS timing, T
is relative to the rising edge of SysClk and T
is relative to the falling edge
of SysClk. In early RAS mode, T
OV
is relative to the rising edge of SysClk. CAS access time assumes a SysClk
50% duty cycle.
2. In early RAS mode, the RAS output delay varies with the 403GC operating frequency. Use the following equation
to determine the worst-case output delay for this signal: T
OV
Max = 12 ns + Tc/4; T
OH
Min remains unchanged.
Valid for T
greater than 30 ns and less than 80 ns.
3. When initiating a system reset, the 403GC pulls the Reset output low for 2048 cycles minimum and then samples
to determine whether Reset is held low externally. Thirty-two cycles after Reset has been sampled as low, the
403GCbegins its internal reset.
4. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted. Output hold times are
measured at 3.47V and T
= 10
°
C.
5. All output hold and float times are guaranteed by design and not tested.
Table 17. 403GC Synchronous Output Timings
25 MHz
T
OHMin
T
OVMax
T
OHMin
T
OVMax
T
OHMin
T
OVMax
T
OH
,
T
OV
Output hold, output valid time
T
OH1
,
T
OV1
A6:31
T
OH2
,
T
OV2
AMuxCAS
T
OH3
,
T
OV3
BusReq
T
OH4
,
T
OV4
CAS0:3
T
OH5
,
T
OV5
CS0:7
T
OH6
,
T
OV6
D0:31
T
OH7
,
T
OV7
DMAA0:3
T
OH8
,
T
OV8
DMADXFER
T
OH9
,
T
OV9
DRAMOE
T
OH10
,
T
OV10
DRAMWE
T
OH11
,
T
OV11
Error
T
OH12
,
T
OV12
HoldAck
T
OH13
,
T
OV13
OE
T
OH14
,
T
OV14
RAS0:3
T
OH15
,
T
OV15
RAS0:3
(Early)
T
OH16
,
T
OV16
Reset
T
OH17
,
T
OV17
R/W
T
OH18
,
T
OV18
TC0:3
T
OH19
,
T
OV19
TS0:6
T
OH20
,
T
OV20
WBE0:3(BE0:3)
T
OH21
,
T
OV21
XAck
3
Output float time
T
OF1
A6:31
T
OF2
CS0:7
T
OF3
D0:31
T
OF4
OE
T
OF5
Reset
T
OF6
R/W
T
OF7
TC0:3
T
OF8
WBE0:3(BE0:3)
3
T
CAS
Available CAS access time
Min
2-1-1-1 access mode (Note )
3-2-2-2 access mode (Note )
1.5T
C
-2.5
Symbol
Parameter
33 MHz
40 MHz
Units
4
3
3
4
2
4
3
3
3
2
4
3
3
3
12
3
3
3
4
3
15
11
12
13
13
16
11
13
11
10
14
12
11
12
22
14
11
13
30
12
13
Max
10
12
11
12
8
12
12
12
4
3
3
4
2
4
3
3
3
3
4
3
3
3
11
3
3
3
4
3
3
Min
2
3
3
3
2
3
3
3
13
11
11
12
11
15
10
11
11
10
12
11
10
11
20
12
10
12
25
11
12
Max
9
10
9
10
7
10
10
10
4
3
3
4
2
4
3
3
3
3
4
3
3
3
11
3
3
3
4
3
3
Min
2
3
3
3
2
3
3
3
11
10
10
11
10
14
9
10
10
9
12
10
9
10
18
12
9
11
22
10
11
Max
9
10
9
10
7
10
10
10
ns
T
OF
Min
2
3
3
3
2
3
3
ns
Max
Min
0.5T
C
- 2.5
1.5T
C
-2.5
Max
Min
0.5T
C
- 2.5
1.5T
C
-2.5
Max
ns
0.5T
C
-2.5
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| 403GC-3BA33C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
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| 403GCX-3BC66C2 | 32-Bit Microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 403GC-3BA33C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
| 403GCX-3BC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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