參數(shù)資料
型號(hào)： 403GC-3BA25C1
元件分類： 復(fù)位半導(dǎo)體
英文描述： 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述： 32位微處理器
文件頁(yè)數(shù)： 4/48頁(yè)
文件大小： 768K
代理商： 403GC-3BA25C1
IBM PowerPC 403GC
4
Instruction Cache Unit
The instruction cache unit (ICU) is a two-way set-
associative 2KB cache memory unit with
enhancements to support branch prediction and
folding. The ICU is organized as 64 sets of 2
lines, each line containing 16 bytes. A separate
bypass path is available to handle cache-
inhibited instructions and to improve performance
during line fill operations.
The cache can send two cached instructions per
cycle to the execution unit, allowing instructions
to be folded out of the queue without interrupting
normal instruction flow. When a branch
instruction is folded and executed in parallel with
another instruction, the ICU provides two more
instructions to replace both of the instructions
just executed so that bandwidth is balanced
between the ICU and the execution unit.
Data Cache Unit
The data cache unit is provided to minimize the
access time of frequently used data items in main
store. The 1KB cache is organized as a two-way
set associative cache. There are 32 sets of 2
lines, each line containing 16 bytes of data. The
cache features byte-writeability to improve the
performance of byte and halfword store
operations.
Cache operations are performed using a write-
back strategy. A write-back cache only updates
locations in main storage that corresponds to
changed locations in the cache. Data is flushed
from the cache to main storage whenever
changed data needs to be removed from the
cache to make room for other data.
The data cache may be disabled for a 128MB
memory region via control bits in the data cache
control register or on a per-page basis if the
MMU is enabled for data translation. A separate
bypass path is available to handle cache-
inhibited data operations and to improve
performance during line fill operations.
Cache flushing and filling are triggered by load,
store, and cache control instructions executed by
the processor. Cache blocks are loaded starting
at the requested fullword, continuing to the end of
the block and then wrapping around to fill the
remaining fullwords at the beginning of the block.
DMA Controller
The four-channel DMA controller manages block
data transfers in buffered, fly-by and memory-to-
memory transfer modes with options for burst-
mode operation. In fly-by and buffered modes,
the DMA controller supports transactions
between memory and peripheral devices.
Each DMA channel provides a control register, a
source address register, a destination address
register, a transfer count register, and a chained
count register. Peripheral set-up cycles, wait
cycles, and hold cycles can be programmed into
each DMA channel control register. Each
channel supports chaining operations. The DMA
status register holds the status of all four
channels.
Exception Handling
Table 2 summarizes the 403GC exception
priorities, types, and classes. Exceptions are
generated by interrupts from internal and
external peripherals, instructions, the internal
timer facility, debug events or error conditions.
Six external interrupt signals are provided on the
403GC: one critical and five general-purpose, all
individually maskable.
All exceptions fall into three basic classes:
asynchronous imprecise exceptions,
synchronous precise exceptions, and
asynchronous precise exceptions. Asynchronous
exceptions are caused by events external to
processor execution, while synchronous
exceptions are caused by instructions.
Except for a system reset or machine check, all
403GC exceptions are handled precisely. Precise
handling implies that the address of the
excepting instruction (synchronous exceptions
other than system call) or the address of the next
sequential instruction (asynchronous exceptions
and system call) is passed to the exception
handling routine. Precise handling also implies
that all instructions prior to the excepting
instruction have completed execution and have
written back their results.
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PDF描述
403GC-3BA33C1 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GC-3BA40C1 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
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403GCX-3BC66C2 32-Bit Microprocessor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
403GC-3BA33C1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GC-3BA40C1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GCX2JC66C2 制造商:IBM 功能描述:38R2233
403GCX-3BC50C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GCX-3BC66C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
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