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參數(shù)資料
| 型號： | 403GC-3BA25C1 |
| 元件分類： | 復位半導體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 768K |
| 代理商： | 403GC-3BA25C1 |
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IBM PowerPC 403GC
2
The 403GC RISC controller consists of a
pipelined RISC processor core and several
peripheral interface units: BIU, DMA controller,
asynchronous interrupt controller, serial port, and
JTAG debug port.
The RISC processor core includes the internal
2KB instruction cache and 1KB data cache,
reducing overhead for data transfers to or from
external memory. The instruction queue logic
manages branch prediction, folding of branch
and condition register logical instructions, and
instruction prefetching to minimize pipeline
stalls.The integrated memory management unit
provides robust memory management and
protection functions, optimized for embedded
environments.
RISC CPU
The RISC core comprises four tightly coupled
functional units: the execution unit (EXU), the
memory management unit (MMU), the data
cache unit (DCU), and the instruction cache unit
(ICU). Each cache unit consists of a data array,
tag array, and control logic for cache
management and addressing. The execution unit
consists of general purpose registers (GPR),
special purpose registers (SPR), ALU, multiplier,
divider, barrel shifter, and the control logic
required to manage data flow and instruction
execution within the EXU.
The EXU handles instruction decoding and
execution, queue management, branch
prediction, and branch folding. The instruction
cache unit passes instructions to the queue in the
EXU or, in the event of a cache miss, requests a
fetch from external memory through the bus
interface unit. The MMU provides translation and
memory protection for instruction and data
accesses, using a unified 64-entry, fully
associative TLB array.
General Purpose Registers
Data transfers to and from the EXU are handled
through the bank of 32 GPRs, each 32 bits wide.
Load and store instructions move data operands
between the GPRs and the data cache unit,
except in the cases of noncacheable data or
cache misses. In such cases the DCU passes
the address for the data read or write to the BIU.
When noncacheable operands are being
transferred, data can pass directly between the
EXU and the BIU, which interfaces to the external
memory being accessed.
Special Purpose Registers
Special purpose registers are used to control
debug facilities, timers, interrupts, the protection
mechanism, memory cacheability, and other
architected processor resources. SPRs are
accessed using move to/from special purpose
register (mtspr/mfspr) instructions, which move
operands between GPRs and SPRs.
Supervisory programs can write the appropriate
SPRs to configure the operating and interface
modes of the execution unit. The condition
register (CR) and machine state register (MSR)
are written by internal control logic with program
execution status and machine state, respectively.
Status of external interrupts is maintained in the
external interrupt status register (EXISR). Fixed-
point arithmetic exception status is available from
the exception register (XER).
Device Control Registers
Device control registers (DCR) are used to
manage I/O interfaces, DMA channels, SRAM
and DRAM memory configurations and timing,
and status/address information regarding bus
errors. DCRs are accessed using move to/from
device control register (mtdcr/mfdcr) instructions,
which move operands between GPRs and DCRs.
Instruction Set
Table 1 summarizes the 403GC instruction set by
categories of operations. Most instructions
execute in a single cycle, with the exceptions of
load/store multiple, load/store string, multiply, and
divide instructions.
Bus Interface Unit
The bus interface unit integrates the functional
controls for data transfers and address
operations other than those which the DMA
controller handles. DMA transfers use the
address logic in the BIU to output the memory
addresses being accessed.
相關PDF資料 |
PDF描述 |
|---|---|
| 403GC-3BA33C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GC-3BA40C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC50C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC66C2 | 32-Bit Microprocessor |
| 403GCX-3BC80C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 403GC-3BA33C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GC-3BA40C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
| 403GCX-3BC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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