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參數(shù)資料
| 型號： | 403GC-3BA33C1 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 768K |
| 代理商： | 403GC-3BA33C1 |
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Data
Sheet
PowerPC 403GC
32-Bit RISC
Embedded Controller
Features
PowerPC
RISC CPU and instruction set
architecture
Glueless interfaces to DRAM, SRAM,
ROM, and peripherals, including byte and
half-word devices
Separate instruction cache and write-back
data cache, both two-way set-associative
Memory management unit
–64-entry, fully associative TLB array
–Variable page size (1KB-16MB)
–Flexible TLB management
Individually programmable on-chip
controllers for:
–Four DMA channels
–DRAM, SRAM, and ROM banks
–External interrupts
Flexible interface to external bus masters
Hardware multiplier and divider
Thirty-two 32-bit general purpose registers
Applications
Set-top boxes
Consumer electronics and video games
Telecommunications and networking
Office automation (printers, copiers, fax)
Personal digital assistants (PDA)
Specifications
25MHz, 33MHz, and 40MHz versions
Interfaces to both 3V and 5V technologies
Low-power 3.3V operation with built-in
power management and stand-by mode
Low-cost 160 lead PQFP package
0.5
μ
m triple-level-metal CMOS
Overview
The PowerPC 403GC 32-bit RISC embedded
controller offers high performance and functional
integration with low power consumption. The
403GC RISC CPU executes at sustained speeds
approaching one cycle per instruction. On-chip
caches and integrated DRAM and SRAM control
functions reduce chip count and design
complexity in systems, while improving system
throughput.
External I/O devices or SRAM/DRAM memory
banks can be directly attached to the 403GC bus
interface unit (BIU). Interfaces for up to eight
memory banks and I/O devices, including a
maximum of four DRAM banks, can be
configured individually, allowing the BIU to
manage devices or memory banks with differing
control, timing, or bus width requirements.
RISC Execution Unit
Cache Unit
Instruction
Cache Unit
Data
4-Channel
DMA
Controller
(Address
and
Control)
Serial
Port
Port
JTAG
DRAM Controller
I/O Controller
Bus Interface Unit
SRAM, ROM, I/O
Controls
Controls
Address
Bus
Data
Bus
Timers
On-chip
Peripheral
Bus
DRAM
Interrupt
Controller
Memory Management Unit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 403GC-3BA40C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC50C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC66C2 | 32-Bit Microprocessor |
| 403GCX-3BC80C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC80C2A | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 403GC-3BA40C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
| 403GCX-3BC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC80C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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