參數(shù)資料
型號: 403GC-3BA33C1
元件分類: 復(fù)位半導(dǎo)體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 32位微處理器
文件頁數(shù): 45/48頁
文件大?。?/td> 768K
代理商: 403GC-3BA33C1
IBM PowerPC 403GC
45
External Master DRAM Burst Write, 3-2-2-2 Page Mode
Bank Register Bit Settings
Notes:
1. XReq, XSize0, XSize1, and XAck are multiplexed with DMAR3, EOT3/TC3, OE, and DMAA3, respectively.
2. XSize0:1 = 11 indicates a burst transfer at the width of the DRAM device.
3. The burst is terminated in cycle 12 by deasserting the XReq input signal. A burst may also be terminated by
deasserting either XSize0 or XSize1.
4. A4, A5, A30, and A31 are multiplexed with WBE0, WBE1, WBE2, and WBE3, respectively.
SLF
ERM
Bus
Width
Ext
Mux
RAS-to-
CAS
Refresh
Mode
Page
Mode
First
Access
Burst
Access
Prechg
Cycles
Refresh
RAS
Refresh
Rate
Bit 13 Bit 14
Bits
15:16
Bit 17
Bit 18
Bit 19
Bit 20
Bits
21:22
Bits
23:24
Bit 25
Bit 26
Bits
27:30
0 or 1
0
10
1
0
0
1
01
01
0
x
xxxx
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
SysClk
R/W
RASx
CAS0:3
DRAMOE
DRAMWE
D0:31
AMuxCAS
HoldReq
HoldAck
XSize0:1
1,2,3
Ext Bus Master
DRAM Control
RAS CAS
Pre-
CAS
XReq BSel
CAS
CAS
CAS CAS
CAS
CAS
11
11
11
Valid Address1 - Ext Master
Valid Data1 - Ext Master
Address2
Address3
Address4
Data2
Data3
Data4
A4:31
4
XReq
3
XAck
17
18
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