參數(shù)資料
型號: 403GC-3BA33C1
元件分類: 復(fù)位半導(dǎo)體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 32位微處理器
文件頁數(shù): 37/48頁
文件大?。?/td> 768K
代理商: 403GC-3BA33C1
IBM PowerPC 403GC
37
SRAM, ROM or I/O Burst Write with Wait, Burst Wait, and Hold
Bank Register Bit Settings
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 19 on page 32 for WBE signal definitions based on bus width.
3. See waveform and note 3 on page 33. WBE signals can be read/write byte enables based on the setting of a
control bit in the IOCR. See waveform and note 3 on page 33.
4. Wait must be programmed to a value
(CSon + WEon + WEoff) and
(CSon + OEon + WEoff).
If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 3 until the Wait
timer expires.
5. If Hold is programmed > 001, all 403GC output signals retain the values shown in cycle 12 until the Hold timer
expires.
SLF
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
Burst
Wait
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits
15:16
Bit 17
Bits
18:21
Bits
22:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits
28:30
0 or 1
1
xx
0
0100
01
0 or 1
0 or 1
0 or 1
0 or 1
001
2
3
4
5
6
7
8
9
10 11 12 13 14
1
A6:29,
1
WBE2[A30],
WBE3[A31]
R/W
CSx
5
WBE0:3
2,3
SysClk
Address1
Addr2
Addr3
Address4
Data1
Data2
Data3
Data4
Wait + 1 Cycles
Hold
Cycles
Cycles
Cycles
WEon=0,1
WEon=0
WEon=1
WEoff=1
WEoff=1
WEoff=1
WEoff=1 WEoff=0
CSon=1
CSon=0
BusError
E
Er
E
Er
OEon=0,1
OEon=0
OEon=1
D0:31
Valid BE
BE
BE
Valid BE
BE0:3
3
OE
4,5
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