- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359865 > 403GC-3BA25C1 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit PDF資料下載
參數(shù)資料
| 型號： | 403GC-3BA25C1 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 768K |
| 代理商： | 403GC-3BA25C1 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
IBM PowerPC 403GC
5
Asynchronous imprecise exceptions include
system resets and machine checks.
Synchronous precise exceptions include most
debug exceptions, program exceptions, data
storage violations, TLB misses, system calls, and
alignment error exceptions. Asynchronous
precise exceptions include the critical interrupt
exception, external interrupts, and internal timer
facility exceptions and some debug events.
Only one exception is handled at a time. If
multiple exceptions occur simultaneously, they
are handled in priority order.
The 403GC processes exceptions as reset,
critical, or noncritical. Four exceptions are
defined as critical: machine check exceptions,
debug exceptions, exceptions caused by an
active level on the critical interrupt pin, and the
first time-out from the watchdog timer.
When a noncritical exception is taken, special
purpose register Save/Restore 0 (SRR0) is
loaded with the address of the excepting
instruction (synchronous exceptions other than
system call) or the next sequential instruction to
be processed (asynchronous exceptions and
system call). If the 403GC is executing a
multicycle instruction (load/store multiple, load/
store string, multiply or divide), the instruction is
terminated and its address stored in SRR0.
Save/Restore Register 1 (SRR1) is loaded with
the contents of the machine state register. The
MSR is then updated to reflect the new context of
the machine. The new MSR contents take effect
beginning with the first instruction of the
exception handling routine.
At the end of the exception handling routine,
execution of a return from interrupt (rfi)
instruction forces the contents of SRR0 and
SRR1 to be loaded into the program counter and
the MSR, respectively. Execution then begins at
the address in the program counter.
The four critical exceptions are processed in a
similar manner. When a critical exception is
taken, SRR2 and SRR3 hold the next sequential
address to be processed when returning from the
exception and the contents of the machine state
register, respectively. After the critical exception
handling routine, return from critical interrupt
(rfci) forces the contents of SRR2 and SRR3 to
be loaded into the program counter and the
MSR, respectively.
Timers
The 403GC contains four timer functions: a time
base, a programmable interval timer (PIT), a
fixed interval timer (FIT), and a watchdog timer.
The time base is a 64-bit counter incremented at
the timer clock rate. The timer clock may be
driven by either an internal signal equal to the
processor clock rate or by a separate external
timer clock pin. No interrupts are generated when
the time base rolls over.
Table 2. 403GC Exception Priorities, Types and Classes
Priority
Exception Type
Exception Class
1
2
System Reset
Machine Check
Asynchronous imprecise
Asynchronous imprecise
Synchronous precise
(except UDE and EXC)
Asynchronous precise
Asynchronous precise
Synchronous precise
3
Debug
4
5
Critical Interrupt
WatchdogTimer Time-out
Program Exception, Data Storage Exception,TLB Miss, and
System Calls
Alignment Exceptions
External Interrupts
Fixed Interval Timer
Programmable Interval Timer
6
7
8
9
Synchronous precise
Asynchronous precise
Asynchronous precise
Asynchronous precise
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 403GC-3BA33C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GC-3BA40C1 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC50C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC66C2 | 32-Bit Microprocessor |
| 403GCX-3BC80C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 403GC-3BA33C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GC-3BA40C1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
| 403GCX-3BC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。