參數(shù)資料
型號: 403GC-3BA25C1
元件分類: 復(fù)位半導(dǎo)體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 32位微處理器
文件頁數(shù): 41/48頁
文件大?。?/td> 768K
代理商: 403GC-3BA25C1
IBM PowerPC 403GC
41
DMA Buffered Single Transfer from Peripheral to 3-Cycle DRAM
Bank Register Bit Settings
DMA Control Register Bit Settings
Notes:
1. DMAR must be sampled inactive at the start of cycle 9 to guarantee a single transfer.
2. Peripheral data bus width must match DRAM bus width.
3. This waveform assumes that the internal address mux is used.
4. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords.
SLF
ERM
Bus
Width
Ext
Mux
RAS-to-
CAS
Refresh
Mode
Page
Mode
First
Access
Burst
Access
Prechg
Cycles
Refresh
RAS
Refresh
Rate
Bit 13 Bit 14
Bits
15:16
Bit 17
Bit 18
Bit 19
Bit 20
Bits
21:22
Bits
23:24
Bit 25
Bit 26
Bits
27:30
0 or 1
0
10
0
0
0
0
01
xx
0
x
xxxx
Transfer Direction Transfer Width Transfer Mode PeripheralSetup Peripheral Wait Peripheral Hold
Bit 2
Bits 4:5
Bits 9:10
Bits 11:12
Bits 13:18
Bits 19-21
1
10
00
00
00 0000
000
DMAR
DMAA
A11:29
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
D0:31
OE
WBE0:3
1
2
3
4
5
6
7
8
9
10
11
12
SysClk
Sync
Sync
BIU
Req
DMA
Ack
RAS
CAS
CAS
Pre-
Charge
Row
Column
Data
Data
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