Revision 1.2
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Processor Programming (
Continued
)
G
3.3.2
The System Register Set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level
programmers who generate operating systems and mem-
ory management programs. Associated with the System
Register Set are certain tables and segments which are
listed in Table 3-5.
System Register Set
The
Control Registers
control certain aspects of the
GXLV processor such as paging, coprocessor functions,
and segment protection.
The
Configuration Registers
are used to define the
GXLV CPU setup including cache management.
The
Debug Registers
provide debugging facilities for the
GXLV processor and enable the use of data access
breakpoints and code execution breakpoints.
The
Test Registers
provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB).
The
Descriptor Table Register
hold descriptors that
manage memory segments and tables, interrupts and
task switching. The tables are defined by corresponding
registers.
The two
Task State Segment Tables
defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.
The
ID Registers
allow BIOS and other software to iden-
tify the specific CPU and stepping.
System Management Mode (SMM) control information is
stored in the
SMM Registers
.
Table 3-5 lists the system register sets along with their
size and function.
Table 3-5. System Register Set
Group
Name
Function
Width
(Bits)
Control
Registers
CR0
System Control
Register
Page Fault Linear
Address Register
Page Directory Base
Register
Time Stamp Counter
Configuration Control
Registers
Linear Breakpoint
Address 0
Linear Breakpoint
Address 1
Linear Breakpoint
Address 2
Linear Breakpoint
Address 3
Breakpoint Status
Breakpoint Control
Cache Test
Cache Test
Cache Test
TLB Test Control
TLB Test Data
General Descriptor Table
Interrupt Descriptor
Table
Local Descriptor Table
GDT Register
IDT Register
LDT Register
Task State Segment
Table
TSS Register Setup
Device Identification
Registers
SMM Address Region
Registers
SMM Header Addresses
Performance Control
Register
32
CR2
32
CR3
32
CR4
CCRn
32
8
Configuration
Registers
Debug
Registers
DR0
32
DR1
32
DR2
32
DR3
32
DR6
DR7
TR3
TR4
TR5
TR6
TR7
GDT
IDT
32
32
32
32
32
32
32
32
32
Test
Registers
Descriptor
Tables
LDT
GDTR
IDTR
LDTR
TSS
16
32
32
16
16
Descriptor
Table
Registers
Task State
Segmentand
Registers
TR
DIRn
16
8
ID
Registers
SMM
Registers
SMARn
8
SMHRn
PCR0
8
8
Performance
Registers