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210
Revision 1.2
Instruction Set (
Continued
)
G
7.1.4
The reg field (Table 7-10) determines which general regis-
ters are to be used. The selected register is dependent on
whether a 16- or 32-bit operation is current and on the
status of the w bit.
reg Field
7.1.4.1
sreg2 Field (ES, CS, SS, DS Register
Selection)
The sreg2 field (Table 7-11) is a 2-bit field that allows one
of the four 286-type segment registers to be specified.
7.1.4.2
sreg3 Field (FS and GS Segment Register
Selection)
The sreg3 field (Table 7-12) is 3-bit field that is similar to
the sreg2 field, but allows use of the FS and GS segment
registers.
7.1.5
The s-i-b fields provide scale factor, indexing and a base
field for address selection. The ss, index and base fields
are described next.
s-i-b Byte (Scale, Indexing, Base)
7.1.5.1
The ss field (Table 7-13) specifies the scale factor used in
the offset mechanism for address calculation. The scale
factor multiplies the index value to provide one of the com-
ponents used to calculate the offset address.
ss Field (Scale Selection)
Table 7-9. General Registers Selected by mod
r/m Fields and w Field
mod
r/m
16-Bit
Operation
32-Bit
Operation
w = 0
w = 1
w = 0
w = 1
11
11
11
11
11
11
11
11
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
DI
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
Table 7-10. General Registers Selected by reg
Field
reg
16-Bit Operation
32-Bit Operation
w = 0
w = 1
w = 0
w = 1
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
DI
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
Table 7-11. sreg2 Field Encoding
sreg2 Field
Segment Register Selected
00
01
10
11
ES
CS
SS
DS
Table 7-12. sreg3 Field Encoding
sreg3 Field
Segment Register Selected
000
001
010
011
100
101
110
111
ES
CS
SS
DS
FS
GS
Undefined
Undefined
Table 7-13. ss Field Encoding
ss Field
Scale Factor
00
01
01
11
x1
x2
x4
x8