Revision 1.2
213
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Instruction Set (
Continued
)
G
7.2.1.2
Standard function 01h (EAX = 1) of the CPUID instruction
returns the processor type, family, model, and stepping
information of the current processor in the EAX register
(see Table 7-18). The EBX and ECX registers are
reserved.
CPUID Instruction with EAX = 00000001h
The standard feature flags supported are returned in the
EDX register as shown in Table 7-19. Each flag refers to a
specific feature and indicates if that feature is present on
the processor. Some of these features have protection
control in CR4. Before using any of these features on the
processor, the software should check the corresponding
feature flag. Attempting to execute an unavailable feature
can cause exceptions and unexpected behavior. For
example, software must check EDX bit 4 before attempt-
ing to use the Time Stamp Counter instruction.
7.2.1.3
Standard function 02h (EAX = 02h) of the CPUID instruc-
tion returns information that is specific to the National
Semiconductor family of processors. Information about
the TLB is returned in EAX as shown in Table 7-20. Infor-
mation about the L1 cache is returned in EDX.
CPUID Instruction with EAX = 00000002h
Table 7-18. EAX, EBX, ECX CPUID Data
Returned when EAX = 1
Register
Returned
Contents
Description
EAX[3:0]
EAX[7:4]
EAX[11:8]
EAX[15:12]
EAX[31:16]
EBX
ECX
xx
4
5
0
-
-
-
Stepping ID
Model
Family
Type
Reserved
Reserved
Reserved
Table 7-19. EDX CPUID Data Returned when
EAX = 1
EDX
Returned
Contents*
Feature Flag
CR4
Bit
EDX[0]
EDX[1]
EDX[2]
EDX[3]
EDX[4]
EDX[5]
1
0
0
0
1
1
FPU On-Chip
Virtual Mode Extension
Debug Extensions
Page Size Extensions
Time Stamp Counter
RDMSR / WRMSR
Instructions
Physical Address
Extensions
Machine Check Exception
CMPXCHG8B Instruction
On-Chip APIC Hardware
Reserved
SYSENTER / SYSEXIT
Instructions
Memory Type Range
Registers
Page Global Enable
-
-
-
-
2
-
EDX[6]
0
-
EDX[7]
EDX[8]
EDX[9]
EDX[10]
EDX[11]
0
1
0
0
0
-
-
-
-
-
EDX[12]
0
-
EDX[13]
0
-
EDX[14]
0
Machine Check
Architecture
Conditional Move
Instructions
Page Attribute Table
Reserved
MMX Instructions
Fast FPU Save and
Restore
Reserved
-
EDX[15]
1
-
EDX[16]
EDX[22:17]
EDX[23]
EDX[24]
0
0
1
0
-
-
-
-
EDX[31:25]
Note:
*0 = Not Supported
0
-
Table 7-20. Standard CPUID with
EAX = 00000002h
Register
Returned
Contents
Description
EAX
xx xx 70 xxh
TLB is 32 entry, 4-way set asso-
ciative, and has 4 KB pages.
The CPUID instruction needs to
be executed only once with an
input value of 02h to retrieve
complete information about the
cache and TLB.
Reserved
Reserved
L1 cache is 16 KB, 4-way set
associated, and has 16 bytes per
line.
EAX
xx xx xx 01h
EBX
ECX
EDX
xx xx xx 80h
Table 7-19. EDX CPUID Data Returned when
EAX = 1 (Continued)
EDX
Returned
Contents*
Feature Flag
CR4
Bit