www.national.com
224
Revision 1.2
Instruction Set (
Continued
)
G
REP OUTS
Output String
F3 6[111w]
-
-
-
-
-
-
-
-
-
24+4n
24+4n\
39+4n
9+2n
b
h,m
REP STOS
Store String
REPE CMPS
Compare String
Find non-match
REPE SCAS
Scan String
Find non-AL/AX/EAX
REPNE CMPS
Compare String
Find match
REPNE SCAS
Scan String
Find AL/AX/EAX
RET
Return from Subroutine
Within Segment
Within Segment Adding Immediate to SP
Intersegment
Intersegment Adding Immediate to SP
Protected Mode: Different Privilege Level
-Intersegment
-Intersegment Adding Immediate to SP
ROL
Rotate Left
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
ROR
Rotate Right
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
RSDC
Restore Segment Register and Descripto
r
RSLDT
Restore LDTR and Descriptor
RSTS
Restore TSR and Descriptor
RSM
Resume from SMM Mode
SAHF
Store AH in FLAGS
SAL
Shift Left Arithmetic
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
SAR
Shift Right Arithmetic
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
SBB
Integer Subtract with Borrow
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
SCAS
Scan String
SETB/SETNAE/SETC
Set Byte on Below/Not Above or Equal/Carry
To Register/Memory
SETBE/SETNA
Set Byte on Below or Equal/Not Above
To Register/Memory
SETE/SETZ
Set Byte on Equal/Zero
To Register/Memory
F3 A[101w]
-
-
-
-
-
-
-
-
-
9+2n
b
h
F3 A[011w]
x
-
-
-
x
x
x
x
x
11+4n
11+4n
b
h
F3 A[111w]
x
-
-
-
x
x
x
x
x
9+3n
9+3n
b
h
F2 A[011w]
x
-
-
-
x
x
x
x
x
11+4n
11+4n
b
h
F2 A[111w]
x
-
-
-
x
x
x
x
x
9+3n
9+3n
b
h
C3
C2 ##
CB
CA ##
-
-
-
-
-
-
-
-
-
3
3
10
10
3
3
13
13
b
g,h,j,k,r
35
35
D[000w] [mod 000 r/m]
D[001w] [mod 000 r/m]
C[000w] [mod 000 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
2
2
2
2
2
2
b
h
D[000w] [mod 001 r/m]
D[001w] [mod 001 r/m]
C[000w] [mod 001 r/m] #
0F 79 [mod sreg3 r/m]
0F 7B [mod 000 r/m]
0F 7D [mod 000 r/m]
0F AA
9E
x
u
u
-
-
-
x
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
x
x
-
-
-
-
-
-
x
x
-
-
-
-
-
-
x
x
-
-
-
-
-
-
x
x
x
x
x
-
-
-
x
x
2
2
2
11
11
11
57
1
2
2
2
11
11
11
57
1
b
h
s
s
s
s
s
s
s
s
D[000w] [mod 100 r/m]
D[001w] [mod 100 r/m]
C[000w] [mod 100 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
u
u
u
x
x
x
x
x
x
1
2
1
1
2
1
b
h
D[000w] [mod 111 r/m]
D[001w] [mod 111 r/m]
C[000w] [mod 111 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
u
u
u
x
x
x
x
x
x
2
2
2
2
2
2
b
h
1[10dw] [11 reg r/m]
1[100w] [mod reg r/m]
1[101w] [mod reg r/m]
8[00sw] [mod 011 r/m] ###
1[110w] ###
A [111w]
x
-
-
-
x
x
x
x
x
1
1
1
1
1
2
1
1
1
1
1
2
b
h
x
-
-
-
x
x
x
x
x
b
h
0F 92 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 96 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 94 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
Table 7-27. Processor Core Instruction Set Summary (Continued)
Instruction
Opcode
Flags
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
O D I
F
F
T
F
S Z
F
A P C
F
F
F
F
F
Clock Count
(Reg/Cache Hit)
Issues