Revision 1.2
221
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Instruction Set (
Continued
)
G
JMP
Unconditional Jump
8-bit Displacement
Full Displacement
Register/Memory Indirect Within Segment
Direct Intersegment
-Call Gate Same Privilege Level
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
Indirect Intersegment
-Call Gate Same Privilege Level
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
JNB/JAE/JNC
Jump on Not Below/Above or Equal/Not Carry
8-bit Displacement
Full Displacement
JNBE/JA
Jump on Not Below or Equal/Above
8-bit Displacement
Full Displacement
JNE/JNZ
Jump on Not Equal/Not Zero
8-bit Displacement
Full Displacement
JNL/JGE
Jump on Not Less/Greater or Equal
8-bit Displacement
Full Displacement
JNLE/JG
Jump on Not Less or Equal/Greater
8-bit Displacement
Full Displacement
JNO
Jump on Not Overflow
8-bit Displacement
Full Displacement
JNP/JPO
Jump on Not Parity/Parity Odd
8-bit Displacement
Full Displacement
JNS
Jump on Not Sign
8-bit Displacement
Full Displacement
JO
Jump on Overflow
8-bit Displacement
Full Displacement
JP/JPE
Jump on Parity/Parity Even
8-bit Displacement
Full Displacement
JS
Jump on Sign
8-bit Displacement
Full Displacement
LAHF
Load AH with Flags
LAR
Load Access Rights
From Register/Memory
LDS
Load Pointer to DS
EB +
E9 +++
FF [mod 100 r/m]
EA [unsigned full offset,
selector]
-
-
-
-
-
-
-
-
1
1
1
1
b
h,j,k,r
1/3
8
1/3
12
22
186
192
126
189
195
129
13
23
187
193
127
190
196
130
FF [mod 101 r/m]
10
73 +
0F 83 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
77 +
0F 87 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
75 +
0F 85 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
7D +
0F 8D +++
-
-
-
-
-
-
-
-
1
1
1
1
r
7F +
0F 8F +++
-
-
-
-
-
-
-
-
1
1
1
1
r
71 +
0F 81 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
7B +
0F 8B +++
-
-
-
-
-
-
-
-
1
1
1
1
r
79 +
0F 89 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
70 +
0F 80 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
7A +
0F 8A +++
-
-
-
-
-
-
-
-
1
1
1
1
r
78 +
0F 88 +++
9F
-
-
-
-
-
-
-
-
1
1
2
1
1
2
r
-
-
-
-
-
-
-
-
-
0F 02 [mod reg r/m]
C5 [mod reg r/m]
-
-
-
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
9
9
a
b
g,h,j,p
h,i,j
4
Table 7-27. Processor Core Instruction Set Summary (Continued)
Instruction
Opcode
Flags
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
O D I
F
F
T
F
S Z
F
A P C
F
F
F
F
F
Clock Count
(Reg/Cache Hit)
Issues