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116
Revision 1.2
Integrated Functions (
Continued
)
G
7
RSVD
DPL
Reserved:
Set to 0.
Data-in to PRE command period (tDPL):
Minimum number of SDRAM clocks from the time the last
write datum is sampled till the bank is precharged:
000 = Reserved
010 = 2 CLK
100 = 4 CLK
001 = 1 CLK
011 = 3 CLK
101 = 5 CLK
Reserved:
Leave unchanged. Always returns a 101h.
Note:
Refer to SDRAM device specifications available from SDRAM manufacturer
’
s for more detailed information
6:4
110 = 6 CLK
111 = 7 CLK
3:0
RSVD
GX_BASE+8414h-8417h
MC_GBASE_ADD (R/W)
Default Value = 00000000h
31:18
17
RSVD
TE
Reserved:
Set to 0.
Test Enable TEST[3:0]:
0 = TEST[3:0] are driven low (normal operation)
1 = TEST[3:0] pins are used to output test information
Test Enable Shared Control Pins:
0 = RASB#, CASB#, CKEB, WEB# (normal operation)
1 = RASB#, CASB#, CKEB, WEB# are used to output test information
Select:
This field is used for debug purposes only. Should be left at zero for normal operation.
Reserved:
Set to 0.
Graphics Base Address:
This field indicates the graphics memory base address, which is program-
mable on 512 KB boundaries. This field corresponds to address bits [29:19].
Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.
16
TECTL
15:12
11
10:0
SEL
RSVD
GBADD
GX_BASE+8418h-841Bh
MC_DR_ADD (R/W)
Default Value = 00000000h
31:10
9:0
RSVD
DRADD
Reserved:
Set to 0.
Dirty RAM Address:
This field is the address index that is used to access the Dirty RAM with the
MC_DR_ACC register. This field does not auto increment.
GX_BASE+841Ch-841Fh
MC_DR_ACC (R/W)
Default Value = 0000000xh
31:2
1
0
RSVD
D
V
Reserved:
Set to 0.
Dirty Bit:
This bit is read/write accessible.
Valid Bit:
This bit is read/write accessible.
Table 4-15. Memory Controller Registers (Continued)
Bit
Name
Description