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| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 44/52頁 |
| 文件大?。?/td> | 687K |
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34
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
Figure 10. Extended Feature Enable Register (EFER)—MSR C000_0080h (Model 9)
Note:
Setting L2D to 1 does not guarantee cache coherency. To
ensure coherency, the processor’s caches must be disabled
(by setting the CD bit of the CR0 register to 1), then flushed
prior to setting L2D to 1.
Write Handling
Control Register
(WHCR)
The AMD-K6-III processor contains a split level-1 (L1) 64-Kbyte
writeback cache organized as a separate 32-Kbyte instruction
cache and a 32-Kbyte data cache with two-way set associativity.
The cache line size is 32 bytes, and lines are read from memory
Table 14. Extended Feature Enable Register (EFER) Definition (Model 9)
Bit
Description
R/W
Function
63–5
Reserved
R
Writing a 1 to any reserved bit causes a general protection
fault to occur. All reserved bits are always read as 0.
If L2D is set to 1, the L2 cache is completely disabled. This bit
is provided for debug and testing purposes. For normal
operation and maximum performance, this bit must be set to
0 (this is the default setting following reset).
This 2-bit field controls the behavior of the processor with
respect to the ordering of write cycles and the EWBE# signal.
EFER[3] and EFER[2] are Global EWBE Disable (GEWBED)
and Speculative EWBE Disable (SEWBED), respectively.
DPE must be set to 1 to enable data prefetching (this is the
default setting following reset). If enabled, cache misses
initiated by a memory read within a 32-byte cache line are
conditionally followed by cache-line fetches of the other line
in the 64-byte sector.
SCE must be set to 1 to enable the usage of the SYSCALL and
SYSRET instructions.
4
L2 Disable (L2D)
R/W
3-2
EWBE Control (EWBEC)
R/W
1
Data Prefetch Enable (DPE)
R/W
0
System Call Extension (SCE)
R/W
1
0
63
S
C
E
Reserved
Description
L2 Disable
EWBE Control
Data Prefetch Enable
System Call Extension
2
3
4
D
P
E
EWBEC
L
2
D
Symbol
L2D
EWBEC
DPE
SCE
Bit
4
3-2
1
0
5
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