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參數(shù)資料
| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計中的應(yīng)用說明 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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20
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
AMD-K6
-2 Processor Model 8/[F:8]
The AMD-K6-2 processor Model 8/[F:8] provides the following
ten MSRs. The first four M
SRs are described in “Standard
MSRs” on page 15. The contents of ECX selects the MSR to be
addressed by the RDMSR and WRMSR instruction.
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Machine-Check Address Register (MCAR)—ECX = 00h
Machine-Check Type Register (MCTR)—ECX = 01h
Test Register 12 (TR12)—ECX = 0Eh
Time Stamp Counter (TSC)—ECX = 10h
Extended Feature Enable Register
(EFER)—ECX = C000_0080h
Write Handling Control Register
(WHCR)—ECX = C000_0082h
SYSCALL/SYSRET Target Address Register
(STAR)—ECX = C000_0081h
UC/WC Cacheability Control Register
(UWCCR)—ECX = C000_0085h
Processor State Observability Register
(PSOR)—ECX = C000_0087h
Page Flush/Invalidate Register
(PFIR)—ECX = C000_0088h
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Extended Feature
Enable Register
(EFER)
The Extended Feature Enable Register (EFER) contains the
control bits that enable the extended features of the processor.
Figure 5 shows the format of the EFER register, and Table 9 on
page 21 defines the function of each bit of the EFER register.
The EFER register is MSR C000_0080h.
Table 8.
SYSCALL/SYSRET Target Address Register (STAR) Definition (Models 8 and 9)
Bit
Description
R/W
Function
63–48
SYSRET CS and SS Selector Base
R/W
During the SYSRET instruction, this field is copied into the CS
register and the contents of this field, plus 1000b, are copied
into the SS register.
During the SYSCALL instruction, this field is copied into the
CS register and the contents of this field, plus 1000b, are
copied into the SS register.
During the SYSCALL instruction, this address is copied into
the EIP and points to the new starting address.
47–32
SYSCALL CS and SS Selector Base
R/W
31–0
Target EIP Address
R/W
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