參數(shù)資料
型號(hào)： 21329
英文描述： AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述： 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說(shuō)明
文件頁(yè)數(shù)： 38/52頁(yè)
文件大?。?/td> 687K
代理商： 21329
28
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
UCn (n=0, 1).
When set to 1, this memory range is defined as
uncacheable (refer to Table 11).
Memory-Range Restrictions.
The following rules regarding the
address alignment and size of each range must be adhered to
when programming the physical base address and physical
address mask fields of the UWCCR register:
I
The minimum size of each range is 128 Kbytes.
The physical base address must be aligned on a 128-Kbyte
boundary.
The physical base address must be
range-size aligned
. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits set to 0 in the physical address
mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask
111_1111_1101_0000b is invalid
I
I
I
Table 12 lists the valid physical address masks and the resulting
range sizes that can be programmed in the UWCCR register.
Table 11. WC/UC Memory Type
WCn
UCn
Memory Type
0
0
No effect on cacheability or write-combining
1
0
Write-combining memory range (uncacheable)
0 or 1
1
Uncacheable memory range
Table 12. Valid Masks and Range Sizes
Masks
Size
111_1111_1111_1111b
128 Kbytes
111_1111_1111_1110b
256 Kbytes
111_1111_1111_1100b
512 Kbytes
111_1111_1111_1000b
1 Mbyte
111_1111_1111_0000b
2 Mbytes
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