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| 型號(hào)： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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6
BIOS Consideration Checklist
AMD-K6
Processor BIOS Design
21329L/0—December 1999
Model-Specific
Registers (MSRs)
I
Only access MSRs implemented in the processor.
Enable Write Allocation by programming the Write
Handling Control Register (WHCR). See
“Write Handling
Control
Register
(WHCR)”
Implementation of Write Allocate in the K86 Processors
Application Note
, order# 21326
for more information.
Note:
The WHCR register as defined in the Model 6, Model 7, and
Model 8/[7:0] has changed in the Model 9.
I
on
page
34
and
the
I
Utilize the information provided in the Processor State
Observability Register (PSOR) to display the correct
processor bus frequency.
Cache Testing
I
The AMD-K6-III processor does not contain MSRs to allow
for testing of the L1 cache. However, the AMD-K6-III
processor does contain a MSR that allows for testing of its L2
cache. This MSR is called L2AAR and it is described in
“Level-2 Cache Array Access Register (L2AAR)” on page 36.
SMM Issues
I
The System Management Mode (SMM) functionality of the
processor is the same as the Pentium processor.
Implement the processor SMM state-save area in a similar
manner as Pentium processors except for the IDT Base and
possibly Pentium processor-reserved areas. See “System
Management Mode (SMM)” on page 13 for more
information.
I
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