參數(shù)資料
型號(hào)： 21329
英文描述： AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述： 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說(shuō)明
文件頁(yè)數(shù)： 39/52頁(yè)
文件大小： 687K
代理商： 21329
Model-Specific Registers (MSRs)
29
21329L/0—December 1999
AMD-K6
Processor BIOS Design
Example.
Suppose that the range of memory from 16 Mbytes to
32 Mbytes is uncacheable, and the 8-Mbyte range of memory on
top of 1 Gbyte is write-combinable. Range 0 is defined as the
uncacheable range, and range 1 is defined as the write-
combining range.
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h) yields
a physical base address 0 field of 000_0000_1000_0000b.
Because the uncacheable range size is 16 Mbytes, the physical
mask value 0 field is 111_1111_1000_0000b, according to Table
12. Bit 1 of the UWCCR register (WC0) is set to 0 and bit 0 of
the UWCCR register is set to 1 (UC0).
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h) yields a
physical base address 1 field of 010_0000_0000_0000b. Because
the write-combining range size is 8 Mbytes, the physical mask
value 1 field is 111_1111_1100_0000b, according to Table 12. Bit
33 of the UWCCR register (WC1) is set to 1 and bit 32 of the
UWCCR register is set to 0 (UC1).
111_1111_1110_0000b
4 Mbytes
111_1111_1100_0000b
8 Mbytes
111_1111_1000_0000b
16 Mbytes
111_1111_0000_0000b
32 Mbytes
111_1110_0000_0000b
64 Mbytes
111_1100_0000_0000b
128 Mbytes
111_1000_0000_0000b
256 Mbytes
111_0000_0000_0000b
512 Mbytes
110_0000_0000_0000b
1 Gbyte
100_0000_0000_0000b
2 Gbytes
000_0000_0000_0000b
4 Gbytes
Table 12. Valid Masks and Range Sizes (continued)
Masks
Size
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