參數(shù)資料
型號(hào): 21329
英文描述: AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述: 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說(shuō)明
文件頁(yè)數(shù): 41/52頁(yè)
文件大?。?/td> 687K
代理商: 21329
Model-Specific Registers (MSRs)
31
21329L/0—December 1999
AMD-K6
Processor BIOS Design
Table 13. Processor-to-Bus Clock Ratios
Page Flush/Invalidate
Register (PFIR)
The AMD-K6-2 processor Model 8/[F:8] contains the Page
Flush/Invalidate Register (PFIR) (see Figure 9 on page 31) that
allows cache invalidation and optional flushing of a specific
4-Kbyte page from the linear address space. The total amount of
L1 cache in the Model 8/[F:8] is 64 Kbytes. Using this register
can result in a much lower cycle count for flushing particular
pages versus flushing the entire cache. When the PFIR is
written to (using the WRMSR instruction), the invalidation
and, optionally, the flushing begins.
Figure 9. Page Flush/Invalidate Register (PFIR)—MSR C000_0088h (Model 8/[F:8])
State of BF[2:0]
Processor-Clock to Bus-Clock Ratio
100b
2.5x
101b
3.0x
110b
6.0x*
111b
3.5x
000b
4.5x
001b
5.0x
010b
4.0x
011b
5.5x
Note:
*
The 2.0x ratio that was supported on Models 6, 7, and 8/[7:0] is no longer
supported on Model 8/[F:8] or Model 9. Instead, if BF[2:0] equals 110b, a
ratio of 6.0x is selected.
LINPAGE
1
0
63
F
/
I
Reserved
Description
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Symbol
LINPAGE
PF
F/I
Bit
31-12
8
0
11
31
12
32
P
F
9 8 7
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