參數(shù)資料
型號(hào)： 21329
英文描述： AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述： 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說(shuō)明
文件頁(yè)數(shù)： 43/52頁(yè)
文件大?。?/td> 687K
代理商： 21329
Model-Specific Registers (MSRs)
33
21329L/0—December 1999
AMD-K6
Processor BIOS Design
AMD-K6
-III
Processor Model 9
The AMD-K6-III processor Model 9 provides the following
eleven MSRs. The first four M
SRs are described in “Standard
MSRs” on page 15. The contents of ECX selects the MSR to be
addressed by the RDMSR and WRMSR instruction.
I
Machine-Check Address Register (MCAR)—ECX = 00h
Machine-Check Type Register (MCTR)—ECX = 01h
Test Register 12 (TR12)—ECX = 0Eh
Time Stamp Counter (TSC)—ECX = 10h
Extended Feature Enable Register
(EFER)—ECX = C000_0080h
Write Handling Control Register
(WHCR)—ECX = C000_0082h
SYSCALL/SYSRET Target Address Register
(STAR)—ECX = C000_0081h
UC/WC Cacheability Control Register
(UWCCR)—ECX = C000_0085h
Processor State Observability Register
(PSOR)—ECX = C000_0087h
Page Flush/Invalidate Register
(PFIR)—ECX = C000_0088h
Level-2 Cache Array Access Register
(L2AAR)—ECX = C000_0089h
I
I
I
I
I
I
I
I
I
I
Extended Feature
Enable Register
(EFER)
Bits 3:0 of the EFER register in the AMD-K6-III processor
Model 9 are identical to the implementation of these bits in the
Model 8/[F:8]. See “Extended Feature Enable Register
(EFER)” on page 20. The L2 Disable bit (L2D)—EFER[4]—is
an addition to the EFER register in the Model 9.
Figure 10 shows the format of the EFER register, and Table 14
defines the function of each bit of the EFER register. The EFER
register is MSR C000_0080h.
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