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| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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8
State of the Processor After INIT
AMD-K6
Processor BIOS Design
21329L/0—December 1999
State of the Processor After INIT
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
SMM base, MSRs, and the CD and NW bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
Table 3.
State of the AMD-K6
-III
Processor Model 9 After RESET
Register
RESET State
Notes
1
2
EDX
EFER
L2AAR
PFIR
PSOR
STAR
UWCCR
WHCR
Notes:
1.
“S” represents the Stepping.
2. Because EFER[4] equals 0 after RESET, the L2 cache is enabled by default after
RESET.
3. “B” represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the
value of the BF[2:0] signals sampled during the falling transition of RESET.
0000_059Sh
0000_0000_0000_0002h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_00SBh
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
1, 3
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