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| 型號(hào)： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 23/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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Built-In Self-Test (BIST)
13
21329L/0—December 1999
AMD-K6
Processor BIOS Design
Built-In Self-Test (BIST)
For all models of the AMD-K6 processor, BIST is run
unconditionally following the falling transition of RESET. The
results of the test are contained in the general purpose register
EAX. If EAX contains 0000_0000h, then BIST was successful. If
the contents of EAX are non-zero, the BIST failed. The internal
resources tested during BIST include the following:
I
L1 instruction and data caches
L2 unified cache (Model 9 only)
Instruction and Data Translation Lookaside Buffers (TLBs)
I
I
System Management Mode (SMM)
This section documents the SMM differences between specified
models of the AMD-K6 processor and the Pentium
processor.
For more information on SMM implementation in the K86
processors, see the
AMD K86 Family BIOS and Software Tools
Developers Guide
, order# 21062.
State-Save Map Differences
The SMM implemented in the AMD-K6 processor differs from
the SMM implemented in the Pentium processor in one way.
The IDT Base location in the AMD-K6 processor is located at
offset FF90h. Pentium has the IDT Base located at offset FF94h.
I/O Trap Dword Differences
The I/O trap dword is located at offset FFA4h. This state-save
area, which is reserved in Pentium, contains information
regarding an I/O instruction that may have been trapped by an
SMI# assertion.
Table 5.
AMD-K6
Processor I/O Trap Dword Configuration at Offset FFA4h
Bits 31–16
I/O Port
Address
Bits 15–4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Rep String
Operation
I/O String Operation
Valid I/O Instruction
Input or Output
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