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XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
47
4.3
T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
When a given channel of the XRT73L02 is configured
to operate in the Remote Loop-Back Mode, the chan-
nel ignores any signals that are input to the TPData
and TNData input pins. The channel receives the in-
coming line signal via the RTIP and RRing input pins.
This data is processed through the entire Receive
Section of the channel and outputs to the Receive
Terminal Equipment via the RPOS, RNEG and RxClk
output pins. Additionally, this data is internally looped
back into the Pulse-Shaping block in the Transmit
Section. At this point, this data is routed through the
remainder of the Transmit Section of the channel and
transmitted out onto the line via the TTIP_(n) and
TRing_(n) output pins.
Figure 29 illustrates the path the data takes in the
XRT73L02 when the chip is configured to operate in
the Remote Loop-Back Mode.
To configure a channel to operate in the Remote
Loop-Back Mode employ either one of the following
two steps
a. Operating in the HOST Mode
To configure Channel (n), write a "1" into the RLB bit-
field and a "0" into the LLB bit-field in Command Reg-
ister CR4.
b. Operating in the Hardware Mode
To configure Channel (n), pull both the RLB input pin
to “High" and the LLB input pin to "Low".
4.4
T
X
OFF F
EATURES
The Transmit Section of each Channel in the
XRT73L02 can be shut off. When this feature is in-
voked, the Transmit Section of the configured channel
is shut-off and the Transmit Output signals TTIP_(n)
and TRing_(n) are tri-stated. This feature is useful for
system redundancy conditions or during diagnostic
testing.
a. Operating in the Hardware Mode
Shut off the Channel (n) Transmit Driver by toggling
the TxOFF_(n) input pin "High". Turn on the Transmit
Driver by toggling the TxOFF_(n) input pin "Low".
b. Operating in the HOST Mode
F
IGURE
29. T
HE
R
EMOTE
L
OOP
-B
ACK
PATH
IN
A
GIVEN
XRT73L02 C
HANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
Notes:
1. (n) = 0 or 1 for respective Channels
2. Serial Processor Interface input pins are shared by the two Channels in HOST Mode and redefined in Hardware Mode.
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch_(n) E3_Ch_(n) LLB_(n)
RLB_(n)
X
X
X
0
1