參數(shù)資料
型號: XRT73L02
廠商: Exar Corporation
英文描述: 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述: 2頻道E3/DS3/STS-1線路接口單元(2通道E3/DS3/STS-1線接口單元)
文件頁數(shù): 2/62頁
文件大?。?/td> 716K
代理商: XRT73L02
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.1.0
á
PRELIMINARY
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
Integrated Pulse Shaping Circuit
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
Contains Transmit Clock Duty Cycle Correction Cir-
cuit on-chip
Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993
Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization
(Optional) and Timing Recovery
Declares and Clears the LOS alarm per ITU-T
G.775 requirements for E3 and DS3 applications
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
Recovered Data can be automatically muted while
the LOS Condition is declared
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
Receiver can be powered down in order to con-
serve power in redundancy designs
PIN OUT OF THE XRT73L02
TxLEV_0
TAOS_0
DVDD_0
DMO_0
DGND_0
AGND_0
DVDD_0
Host/(HW)
RxClk_0
RNEG_0
RPOS_0
DGND_0
RLOS_0
LCV_0
RLOL_0
EXClk_0
CS/(ENDECDIS)
SClk/(RxOFF_1)
SDI/(RxOFF_0)
SDO/(E3_Ch_0)
S
I
L
L
R
A
R
R
A
R
R
A
R
R
A
R
L
L
E
S
TxLEV_1
TAOS_1
DVDD_1
DMO_1
DGND_1
AGND_1
DVDD_1
LOSMUTEN
RxClk_1
RNEG_1
RPOS_1
DGND_1
RLOS_1
LCV_1
RLOL_1
EXClk_1
VDD
GND
REGR/(RxClkINV)
STS-1/DS3_Ch_1
80 Lead TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
4
8
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
T
T
T
T
M
M
A
T
T
A
A
T
T
A
M
M
T
T
T
T
相關PDF資料
PDF描述
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
相關代理商/技術參數(shù)
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