參數(shù)資料
型號(hào): XRT73L02
廠商: Exar Corporation
英文描述: 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述: 2頻道E3/DS3/STS-1線路接口單元(2通道E3/DS3/STS-1線接口單元)
文件頁數(shù): 17/62頁
文件大?。?/td> 716K
代理商: XRT73L02
á
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
13
73
TTIP_0
O
Transmit TTIP Output - Channel 0:
The XRT73L02 uses this pin with TRing_0 to transmit a bipolar line signal via
a 1:1 transformer.
74
AVDD_0
****
Transmit Analog VDD - Channel 0
75
MRing_0
I
Monitor Ring Input - Channel 0:
The bipolar line output signal from TRing_0 is connected to this pin via a 270-
ohm resistor to check for line driver failure. This pin is internally pulled "High".
76
MTIP_0
I
Monitor Tip Input - Channel 0:
The bipolar line output signal from TTIP_0 is connected to this pin via a 270-
ohm resistor to check for line driver failure. This pin is internally pulled "High".
77
TNData_0
I
Transmit Negative Data Input - Channel 0:
The XRT73L02 samples this pin on the falling edge of TxClk_0. If it samples a
"1", then it generates and transmits a negative polarity pulse to the line.
N
OTES
:
1. This input pin is ignored and tied to GND if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
2. If operating in the HOST Mode, it can be configured to sample the
TNData_0 pin on either the rising or falling edge of TxClk_0.
78
TPData_0
I
Transmit Positive Data Input - Channel 0:
The XRT73L02 samples this pin on the falling edge of TxClk_0. If it samples a
"1", then it generates and transmits a positive polarity pulse to the line.
N
OTES
:
1. The data should be applied to this input pin if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
2. If the XRT73L02 is operating in the HOST Mode it can be configured
to sample the TPData_0 pin on either the rising or falling edge of
TxClk_0.
79
TxClk_0
I
Transmit Clock Input for TPData and TNData - Channel 0:
This input pin must be driven at 34.368 MHz for E3 applications, 44.736 MHz
for DS3 applications or 51.84 MHz for SONET STS-1 applications. The
XRT73L02 uses this signal to sample the TPData_0 and TNData_0 input pins.
By default, the XRT73L02 is configured to sample these two pins on the falling
edge of this signal.
If operating in the HOST Mode, the XRT73L02 can be configured to sample
the TPData_0 and TNData_0 input pins on either the rising or falling edge of
TxClk_0.
80
TxOFF_0
I
Transmitter OFF Input - Channel 0:
Setting this input pin "High" configures the XRT73L02 to turn off the Transmit
Section of Channel 0. In this mode, the TTIP_0 and TRing_0 outputs is tri-
stated.
N
OTES
:
1. This input pin controls the TTIP_0 and TRing_0 outputs even when
the XRT73L02 is operating in the HOST Mode.
2. For HOST Mode Operation, tie this pin to GND if the Transmitter is
intended to be turned off via the Microprocessor Serial Interface.
PIN DESCRIPTION
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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