參數(shù)資料
型號(hào)： XRT73L02
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁(yè)數(shù)： 50/62頁(yè)
文件大小： 716K
代理商： XRT73L02
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.1.0
á
PRELIMINARY
46
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin “High"
and the RLB_(n) input pin “Low".
N
OTE
:
The Analog Local Loop-Back mode does not work if
the transmitter is turned off via the TxOFF feature.
4.2
T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
.
When a given channel in the XRT73L02 is configured
to operate in the Digital Local Loop-Back Mode, the
channel ignores any signals that are input to the RTIP
and RRing input pins. The Transmitting Terminal
Equipment transmits clock and data into the
XRT73L02 via the TPData, TNData and TxClk input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder block. At this point, this data loops back to
the HDB3/B3ZS Decoder block. After this post-Loop-
Back data has been processed through the HDB3/
B3ZS Decoder block, it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS, RNEG
and RxClk output pins.
Figure 28 illustrates the path the data takes in the
XRT73L02 when the chip is configured to operate in
the Digital Local Loop-Back Mode.
To configure a channel to operate in the Digital Local
Loop-Back Mode, employ either one of the following
two-steps:
a. Operating in the HOST Mode
To configure Channel (n), write a “1" into both the
LLB and RLB bit-fields in Command Register CR4-
(n), as illustrated below.
b. Operating in the Hardware Mode
To configure Channel (n), pull both the LLB input pin
and the RLB input pin “High".
N
OTE
:
The Digital Local Loop-Back mode works even if the
transmitter is turned off via the TxOFF feature.
F
IGURE
28. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
IN
A
GIVEN
CHANNEL
OF
THE
XRT73L02
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
Notes:
1. (n) = 0 or 1 for respective Channels
2. Serial Processor Interface input pins are shared by the two Channels in HOST Mode and redefined in Hardware Mode.
COMMAND REGISTER CR4-(N)
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch_(n) E3_Ch_(n) LLB_(n) RLB_(n)
X
X
X
1
1
相關(guān)PDF資料
PDF描述
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT73L02M 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT73L02MIV 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MIV-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT73L02MIVTR-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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