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參數(shù)資料
| 型號： | XRT73L02 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 13/62頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XRT73L02 |
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XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
9
42
REGR/
(RxClkNV)
I
Register Reset Input pin (Invert RxClk_(n)) Output - Select):
The function of this pin depends upon whether the XRT73L02 is operating in
the HOST Mode or in the Hardware Mode.
N
OTE
:
This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input pin:
Setting this input pin "Low" causes the XRT73L02 to reset the contents of the
Command Registers to their default settings and default operating configura-
tion.
In the Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Channels in
the XRT73L02 to invert their RxClk_(n) clock output signals and configures
Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n)
output pins on the falling edge of RxClk_(n).
Setting this pin "Low" configures Channel (n) to output the recovered data via
the RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n).
43
GND
****
ExClk Reference GND
44
VDD
****
ExClk Reference VDD
45
EXClk_1
I
External Reference Clock Input - Channel 1:
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock sig-
nal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 appli-
cations.
The Clock Recovery PLL in Channel 1 uses this signal as a Reference Signal
for Declaring and Clearing the Receive Loss of Lock Alarm.
N
OTES
:
1. It is permissible to use the same clock which is also driving the TxClk
input pin.
2. It is permissible to operate the two Channels at different data rates
46
RLOL_1
O
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "High" if Channel 1 of the XRT73L02 has detected a
Loss of Lock Condition. Channel 1 declares an LOL (Loss of Lock) Condition
if the recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk_(n) input pin) by more than 0.5%.
47
LCV_1
O
Line Code Violation Indicator - Channel 1:
Whenever the Receive Section of Channel 1 detects a Line Code Violation, it
pulses this output pin "High". This output pin remains "Low" at all other times.
N
OTE
:
The XRT73L02 outputs an NRZ pulse via this output pin. It is advis-
able to sample this output pin via the RxClk_1 clock output signal.
48
RLOS_1
O
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "High" if Channel 1 in the XRT73L02 has detected a
Loss of Signal Condition in the incoming line signal.
The criteria the XRT73L02 uses to declare an LOS Condition depends upon
whether it is operating in the E3 or STS-1/DS3 Mode.
49
DGND_1
****
Receive Digital Ground - Channel 1
PIN DESCRIPTION
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02M | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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