- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376461 > XRT73L02 (Exar Corporation) 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT73L02 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 31/62頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XRT73L02 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
á
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
27
1. In this mode the Transmit Logic Block ignores the
TNData input pin.
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 9 illustrates the behavior of the TPData and
TxClk_(n) signals when the Transmit Logic Block has
been configured to accept Single-Rail data from the
Terminal Equipment.
2.2
T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IR
-
CUITRY
The on-chip Pulse-Shaping circuitry in the Transmit
Section of each Channel of the XRT73L02 generates
pulses of the appropriate shapes and width to meet
the applicable pulse template requirements. The
widths of these output pulses are defined by the width
of the half-period pulses in the TxClk_(n) signal.
However, if the widths of the pulses in the TxClk_(n)
clock signal are allowed to vary significantly, this
could jeopardize the chip's ability to generate Trans-
mit Output pulses of the appropriate width, thereby
not meeting the Pulse Template requirement specifi-
cation. Consequently, the chip's ability to generate
compliant pulses could depend upon the duty cycle of
the clock signal applied to the TxClk_(n) input pin.
The Transmit Clock Duty Cycle Adjust Circuitry ac-
cepts clock pulses via the TxClk_(n) input pin at duty
cycles ranging from 30% to 70% and converts them
to a 50% duty cycle.
2.3
T
HE
HDB3/B3ZS E
NCODER
B
LOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remote Ter-
minal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist in the line
signal.
2.3.1
B3ZS Encoding
If the XRT73L02 has been configured to operate in
the DS3 or SONET STS-1 Modes, the HDB3/B3ZS
Encoder blocks operate in the B3ZS Mode. When the
Encoder is operating in this mode it parses through
and searches the Transmit Binary Data Stream from
the Transmit Logic Block for the occurrence of three
(3) consecutive zeros (e.g., "000"). If the B3ZS En-
coder finds an occurrence of three consecutive zeros,
then it substitutes these three "0’s" with either a "00V"
or a "B0V" pattern.
"B" represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code.
"V" represents a Bipolar Violation (e.g., a Bipolar
pulse that violates the Alternating Polarity require-
ments of the AMI line code).
The B3ZS Encoder decides whether to substitute
with either the "00V" or the "B0V" pattern in order to
insure that an odd number of Bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 10 illustrates the B3ZS Encoder at work with
two separate strings of three or more consecutive ze-
ros.
F
IGURE
9. T
HE
B
EHAVIOR
OF
THE
TPD
ATA
AND
T
X
C
LK
I
NPUT
S
IGNALS
WHILE
THE
T
RANSMIT
L
OGIC
B
LOCK
IS
A
CCEPTING
S
INGLE
-R
AIL
D
ATA
FROM
THE
T
ERMINAL
E
QUIPMENT
TxClk
TPData
Data 1 1 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02M | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。