XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
á
85
Bit 0 - FERF on AIS
This Read/Write bit-field allows the user to configure the Transmit DS3/E3 Framer block to generate a Yellow
Alarm if the Near-End Receive DS3/E3 Framer block (within the same channel) detects an AIS (Alarm
Indication Signal) Condition.
Writing a "1" to this bit-field enables this feature. Writing a "0" to this bit-field disables this feature.
N
OTE
:
For more information on this feature, refer to
Section 4.2.4.2.1.8
.
2.3.5.2
Transmit DS3 FEAC Configuration & Status Register
Bit 4 - Tx FEAC Interrupt Enable
This Read-Write bit-field permits the user to enable or disable the Transmit FEAC Interrupt.
Setting this bit-field to “0” disables this interrupt.
Conversely, setting this bit-field to “1” enables this interrupt.
Bit 3 - TxFEAC Interrupt Status
This Reset-upon-Read bit-field indicates whether or not the FEAC Message Transmission Complete interrupt
has occurred since the last read of this register. This interrupt will occur once the Transmit FEAC Processor
has finished its 10th transmission of the 16 bit FEAC Message (6 bit FEAC Code word + 10 framing bits). The
purpose of this interrupt is to let the local μP know that the Transmit FEAC Processor has completed its
transmission of its latest FEAC Message and is now ready to transmit another FEAC Message.
If this bit-field is "0", then the FEAC Message Transmission Complete interrupt has NOT occurred since the last
read of this register.
If this bit-field is “1”, then the FEAC Message Transmission Complete interrupt has occurred since the last read
of this register.
N
OTE
:
For more information on the Transmit FEAC Processor, refer to
Section 4.2.3.1
.
Bit 2 - TxFEAC Enable
This Read/Write bit-field allows the user to enable or disable the Transmit FEAC Processor. The Transmit
FEAC Processor will NOT function until it has been enabled.
Writing a "0" to this bit-field disables the Transmit FEAC Processor. Writing a "1" to this bit-field enables the
Transmit FEAC Processor.
Bit 1 - TxFEAC Go
This bit-field allows the user to invoke the Transmit FEAC Message command. Once this command has been
invoked, the Transmit FEAC Processor will do the following:
Encapsulate the 6 bit FEAC code word, from the Tx DS3 FEAC Register (Address = 0x32) into a 16 bit FEAC
Message
Serially transmit this 16-bit FEAC Message to the far-end receiver via the outbound DS3 data-stream,
recursively. After the 10
th
transmission, generate the TxFEAC complete interrupt and continue transmitting.
N
OTE
:
For more information on the Transmit FEAC Processor, refer to
Section 4.2.3.1
.
Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
Tx FEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
GO
TxFEAC
Busy
RO
RO
RO
R/W
RUR
R/W
R/W
RO
0
0
0
0
0
0
0
0