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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
230
Servicing the Change of State on Receive AIS Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
It will assert the Interrupt Request output pin (Int) by driving it "Low".
It will set Bit 5 (AIS Interrupt Status) within the RxDS3 Interrupt Status Register, to “1”, as indicated below.
Whenever the Terminal Equipment encounters a Change in AIS on Receive interrupt, it should do the following.
1.
It should determine the current state of the AIS condition. Recall, that this interrupt can generated, when-
ever the XRT72L50 Framer declares or clears the AIS defects. Hence, the current state of the AIS defect
can be determined by reading the state of Bit 7 (RxAIS), within the RxDS3 Configuration & Status Regis-
ters, as illustrated below
If the AIS Condition is TRUE
1.
The Local Terminal Equipment should transmit a FERF (Far-End Receive Failure) to the Remote Terminal
Equipment. The XRT72L50 Framer IC automatically supports this action via the FERF-upon-AIS feature.
2.
It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE), to the Remote Terminal,
indicating that a Service Affecting condition has been detected in the Local Terminal Equipment.
If the AIS Condition is FALSE
1.
The Local Terminal Equipment should cease transmitting a FERF (Far-End Receive Failure) indicator to
the Remote Terminal Equipment. The XRT72L50 Framer IC automatically supports this action via the
FERF-upon-AIS feature.
2.
It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE) to the Remote Terminal,
indicates that the Service Affecting condition no longer exists.
4.3.6.2.4
The Change of State of Receive Idle Interrupt
If the Change of State on Receive Idle Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt in response to either of the following conditions.
1.
When the XRT72L50 Framer IC detects an Idle pattern, in the incoming DS3 data stream, and
2.
When the XRT72L50 Framer IC no longer detects the Idle pattern in the incoming DS3 data stream.
Conditions causing the XRT72L50 Framer IC to declare an Idle condition
If the Receive DS3 Framer block (within the XRT72L50 Framer IC) detects at least 63 DS3 frames, which
contains the Idle pattern.
RxDS3 Interrupt Status Register (Address = 0x13)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
1
0
0
0
0
0
RxDS3 Configuration & Status Register (Address = 0x10)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxAIS
RxLOS
RxIdle
RxOOF
Reserved
Framing On
Parity
FSync
Algo
MSync
Algo
RO
RO
RO
RO
RO
R/W
R/W
R/W
0
0
0
0
X
0
0
0