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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
106
2.3.7.5
Transmit E3 FAS Mask Register - 0 (ITU-T G.751)
Bits 4 - 0, TxFAS_Error_Mask_Upper[4:0]
This Read/Write bit-field permits the user to insert errors into the upper five bits of the Framing Alignment
Signal, FAS of each outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to
transmission, the Transmit E3 Framer block reads in the upper five (5) bits of the FAS value, and performs an
XOR operation with it and the contents of this register. The results of this operation are written back into the
upper five (5) bits of the FAS value, in each outbound E3 frame. Consequently, to insure errors are not injected
into the FAS of the outbound E3 frames, the contents of this register must be set to all "0’s" (the default value).
2.3.7.6
Transmit E3 FAS Error Mask Register - 1 (ITU-T G.751)
Bits 4 - 0, TxFAS_Error_Mask_Lower[4:0]
This Read/Write bit-field permits the user to insert errors into the lower five bits of the Framing Alignment
Signal, FAS of each outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to
transmission, the Transmit E3 Framer block reads in the lower five (5) bits of the FAS value, and performs an
XOR operation with it and the contents of this register. The results of this operation are written back into the
lower five (5) bits of the FAS value, in each outbound E3 frame. Consequently, to insure errors are not injected
into the FAS of the outbound E3 frames, the contents of this register must be set to all "0’s" (the default value).
2.3.7.7
Transmit E3 BIP-4 Error Mask Register (ITU-T G.751)
Bits 3 - 0: TxBIP-4 Mask[3:0]
This Read/Write bit-field permits the user to insert errors into the BIP-4 value within each outbound E3 frame.
The user may wish to do this for equipment testing purposes. Prior to transmission, the Transmit DS3/E3
Framer block reads in the BIP-4 value, and performs an XOR operation with it and the contents of this register.
The results of this operation are written back into the BIP-4 nibble position, in each outbound E3 frame.
Consequently, to insure errors are not injected into the BIP-4 value of the outbound E3 frames, the contents of
this register must be set to all "0’s" (the default value).
TxE3 FAS Error Mask Register - 0 (Address = 0x48)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
TxFAS_Error_Mask_Upper[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TxE3 FAS Error Mask Register - 1 (Address = 0x49)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
TxFAS_Error_Mask_Lower[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TxE3 BIP-4 Error Mask Register (Address = 0x4A)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
TxBIP-4 Mask[3:0]
RO
RO
RO
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0