參數(shù)資料
型號(hào)： XRT16C854
廠商： Exar Corporation
英文描述： 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
中文描述： 2.97V至5.5V四路UART的128字節(jié)FIFO
文件頁(yè)數(shù)： 7/54頁(yè)
文件大?。?/td> 485K
代理商： XRT16C854
xr
REV. 3.0.1
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
7
CDA#
CDB#
CDC#
CDD#
64
18
31
49
9
27
43
61
99
32
49
83
I
UART channels A-D Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used.
RIA#
RIB#
RIC#
RID#
63
19
30
50
8
28
42
62
98
33
48
84
I
UART channels A-D Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used.
ANCILLARY SIGNALS
XTAL1
25
35
40
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
26
36
41
O
Crystal or buffered clock output.
16/68#
-
31
36
Intel or Motorola Bus Select (input with internal pull-up).
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will
operate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.
Motorola bus interface is not available on the 64 pin package.
CLKSEL
21
30
35
I
Baud-Rate-Generator Input Clock Prescaler Select for channels A-
D. This input is only sampled during power up or a reset. Connect
to VCC for divide by 1 and GND for divide by 4. MCR[7] can over-
ride the state of this pin following a reset or initialization. See MCR
bit-7 and
Figure 6
in the Baud Rate Generator section.
CHCCLK
-
-
42
I
This input provides the clock for UART channel C. An external
16X baud clock or the crystal oscillator’s output, XTAL2, must be
connected to this pin for normal operation. This input may also be
used with MIDI (Musical Instrument Digital Interface) applications
when an external MIDI clock is provided.
RESET
(RESET#)
27
37
43
I
When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes the Reset pin (active high). In this case, a 40 ns mini-
mum logic 1 pulse on this pin will reset the internal registers and all
outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset
period (
Table 18
). When 16/68# pin is at a logic 0 for Motorola bus
interface, this input becomes Reset# pin (active low). This pin
functions similarly, but instead of a logic 1 pulse, a 40 ns minimum
logic 0 pulse will reset the internal registers and outputs.
Motorola bus interface is not available on the 64 pin package.
VCC
4, 35, 52
13, 47,
64
10, 61,
86
Pwr
2.97V to 5.5V power supply. All input pins, except XTAL1, are 5V
tolerant.
GND
14, 28,
45, 61
6, 23, 40,
57
20, 46,
71, 96
Pwr
Power supply common, ground.
Pin Description
N
AME
64-LQFP
P
IN
#
68-PLCC
P
IN
#
100-QFP
P
IN
#
T
YPE
D
ESCRIPTION
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