參數(shù)資料
型號(hào)： XRT16C854
廠(chǎng)商： Exar Corporation
英文描述： 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
中文描述： 2.97V至5.5V四路UART的128字節(jié)FIFO
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 485K
代理商： XRT16C854
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
26
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
SEE”RECEIVER” ON PAGE 15.
4.2
Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 14.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A.
The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C.
The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C854 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR
or
RX FIFO.
B.
LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C.
LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D.
LSR BIT-5 indicates THR is empty.
E.
LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F.
LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode
or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. These LSR bits generate an interrupt immediately when
the character has been received.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
Receive Holding Register (RHR) - Read- Only
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