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參數(shù)資料
| 型號： | XRT16C854 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO |
| 中文描述： | 2.97V至5.5V四路UART的128字節(jié)FIFO |
| 文件頁數(shù)： | 4/54頁 |
| 文件大小： | 485K |
| 代理商： | XRT16C854 |
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XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
4
PIN DESCRIPTIONS
Pin Description
N
AME
64-LQFP
P
IN
#
68-PLCC
P
IN
#
100-QFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
22
23
24
32
33
34
37
38
39
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transac-
tion.
D7
D6
D5
D4
D3
D2
D1
D0
60
59
58
57
56
55
54
53
5
4
3
2
1
68
67
66
95
94
93
92
91
90
89
88
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(N.C.)
40
52
66
I
When 16/68# pin is at logic 1, the Intel bus interface is selected
and this input becomes read strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data byte from
an internal register pointed by the address lines [A2:A0], puts the
data byte on the data bus to allow the host processor to read it on
the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input is not used.
IOW#
(R/W#)
9
18
15
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input becomes read (logic 1) and write (logic 0)
signal. Motorola bus interface is not available on the 64 pin pack-
age.
CSA#
(CS#)
7
16
13
I
When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSB#
(A3)
11
20
17
I
When 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSC#
(A4)
38
50
64
I
When 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT16L2552 | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XRT3591 | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591B | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591BID | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591BIP | SINGLECHIP V. 35 TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT16L2552 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XRT2588CN | 制造商:Exar Corporation 功能描述: |
| XR-T2713CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Subscriber Line Metering/Monitoring Circuit |
| XR-T3588 | 制造商:EXAR 制造商全稱:EXAR 功能描述:V.35 Interface Receiver/Transmitter |
| XR-T3588-89ES | 制造商:EXAR 制造商全稱:EXAR 功能描述:XR-T3588/89 Evaluation System |
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