參數(shù)資料
型號： XRT16C854
廠商： Exar Corporation
英文描述： 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
中文描述： 2.97V至5.5V四路UART的128字節(jié)FIFO
文件頁數(shù)： 53/54頁
文件大小： 485K
代理商： XRT16C854
xr
REV. 3.0.1
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
F
EATURES
.....................................................................................................................................................1
A
PPLICATIONS
...............................................................................................................................................1
F
IGURE
1. XR16C854 B
LOCK
D
IAGRAM
........................................................................................................................................... 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
100-
PIN
QFP P
ACKAGES
I
N
16
AND
68 M
ODE
....................................................................... 2
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
F
OR
PLCC P
ACKAGES
I
N
16
AND
68 M
ODE
AND
LQFP P
ACKAGES
............................................... 3
ORDERING
INFORMATION
................................................................................................................................3
PIN DESCRIPTIONS .........................................................................................................4
1.0 PRODUCT DESCRIPTION ....................................................................................................................9
2.0 FUNCTIONAL DESCRIPTIONS ..........................................................................................................10
2.1 CPU INTERFACE ........................................................................................................................................... 10
F
IGURE
4. XR16C854/854D T
YPICAL
I
NTEL
/M
OTOROLA
D
ATA
B
US
I
NTERCONNECTIONS
................................................................. 10
2.2 5-VOLT TOLERANT INPUTS ......................................................................................................................... 11
2.3 DEVICE RESET .............................................................................................................................................. 11
2.4 DEVICE IDENTIFICATION AND REVISION .................................................................................................. 11
2.5 CHANNEL SELECTION ................................................................................................................................. 11
T
ABLE
1: C
HANNEL
A-D S
ELECT
IN
16 M
ODE
................................................................................................................................. 11
T
ABLE
2: C
HANNEL
A-D S
ELECT
IN
68 M
ODE
................................................................................................................................. 11
2.6 CHANNELS A-D INTERNAL REGISTERS .................................................................................................... 12
2.7 INT OUPUTS FOR CHANNELS A-D .............................................................................................................. 12
T
ABLE
3: INT P
INS
O
PERATION
FOR
T
RANSMITTER
FOR
C
HANNELS
A-D ......................................................................................... 12
T
ABLE
4: INT P
IN
O
PERATION
FOR
R
ECEIVER
FOR
C
HANNELS
A-D................................................................................................. 12
2.8 DMA MODE .................................................................................................................................................... 12
T
ABLE
5: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
FOR
C
HANNELS
A-D ........................................................... 13
2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 13
F
IGURE
5. T
YPICAL
OSCILATOR
CONNECTIONSL
............................................................................................................................... 13
2.10 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 13
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
..................................................................................................................... 14
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
...................................................................... 14
2.11 TRANSMITTER ............................................................................................................................................. 14
2.11.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 14
2.11.2 TRANSMITTER OPERATION IN NON-FIFO MODE................................................................................................ 14
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
.............................................................................................................. 15
2.11.3 TRANSMITTER OPERATION IN FIFO MODE......................................................................................................... 15
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
..................................................................................... 15
2.12 RECEIVER .................................................................................................................................................... 15
2.12.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 16
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
.................................................................................................................... 16
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
....................................................................... 16
2.13 AUTO RTS HARDWARE FLOW CONTROL ............................................................................................... 17
2.14 AUTO RTS HYSTERESIS ........................................................................................................................... 17
2.15 AUTO CTS FLOW CONTROL ..................................................................................................................... 17
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
....................................................................................................... 18
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 19
T
ABLE
7: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
............................................................................................................... 19
2.17 SPECIAL CHARACTER DETECT ............................................................................................................... 19
2.18 INFRARED MODE ........................................................................................................................................ 19
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
.......................................................................... 20
2.19 SLEEP MODE WITH AUTO WAKE-UP ...................................................................................................... 20
2.20 INTERNAL LOOPBACK .............................................................................................................................. 21
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNELS
A-D..................................................................................................................... 22
3.0 UART INTERNAL REGISTERS ...........................................................................................................23
T
ABLE
8: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 23
T
ABLE
9: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1......................................... 24
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................26
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 26
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 26
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 26
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 26
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