參數(shù)資料
型號： XRT16L2552
廠商： Exar Corporation
英文描述： 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述： 2.25V至5.5V的杜阿爾特16字節(jié)FIFO
文件頁數(shù)： 1/47頁
文件大?。?/td> 413K
代理商： XRT16L2552
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
xr
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
MAY 2005
GENERAL DESCRIPTION
REV. 1.1.1
The XR16L2552 (L2552) is a dual universal
asynchronous receiver and transmitter (UART) with 5
volt tolerant inputs. The XR16L2552 is an improved
version of the ST16C2552 UART with lower operating
voltages and 5 volt tolerant inputs. The L2552
provides enhanced UART functions with 16 byte TX
and RX FIFOs, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem control interface. Onboard status registers
provide the user with error indications and
operational status. Indepedendent programmable
baud rate generators are provided to select transmit
and receive clock rates up to 3.125Mbps. An internal
loop-back capability allows onboard diagnostics. The
L2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to write the control registers for both UARTs
concurrently and selection of the Multi-Function
output (Baudout#, OP2#, or RXRDY#).
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
2.25 to 5.5 Volt Operation
5 Volt Tolerant Inputs
Pin-to-pin and functionally compatible to National
PC16552
Pin-to-pin Compatible to Exar’s ST16C2552,
XR16L2752 and XR16C2852 in the 44-PLCC
2 Independent UART Channels
■
Up to 3.125Mbps with external clock of 50 MHz
■
Register Set Compatible to 16C550
■
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
■
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
■
4 selectable RX FIFO Trigger Levels
■
Automatic RTS/CTS hardware flow control
■
Automatic XonXoff software flow control
■
Wireless infrared encoder/decoder
■
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
■
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
■
Multi-Function output allows more package
functions with fewer I/O pins
Concurrent write to Channels A and B
Crystal oscillator or external clock input
48-TQFP (7x7x1.0 mm)
and 44-PLCC packages
F
IGURE
1. XR16L2552 B
LOCK
D
IAGRAM
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
XTAL1
XTAL2
Crystal Osc/Buffer
TXA
8-bit Data
Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG
TX & RX
UART
Regs
2.25 to 5.5 Volt VCC
GND
2552BLK
UART Channel B
(same as Channel A)
A2:A0
D7:D0
IOR#
CS#
CHSEL
INTA
INTB
IOW#
Reset
TXRDY# A/B
RXRDY# A/B
(48-TQFP Only)
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
RXA
Modem Control Logic
DTR#A/B, RTS#A/B
TXB
RXB
* 5 Volt Tolerant Inputs
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