參數(shù)資料
型號: XRT16L2552
廠商: Exar Corporation
英文描述: 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述: 2.25V至5.5V的杜阿爾特16字節(jié)FIFO
文件頁數(shù): 20/47頁
文件大?。?/td> 413K
代理商: XRT16L2552
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
xr
REV. 1.1.1
20
2.20
The L2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode
is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/
CTS is not supported during internal loopback.
Internal Loopback
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B
TXA/TXB
RXA/RXB
M
I
RTSA#/RTSB#
MCR bit-4=1
VCC
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
VCC
(OP2A#/OP2B#)
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