參數(shù)資料
型號(hào)： XRT16L2552
廠商： Exar Corporation
英文描述： 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述： 2.25V至5.5V的杜阿爾特16字節(jié)FIFO
文件頁(yè)數(shù)： 33/47頁(yè)
文件大?。?/td> 413K
代理商： XRT16L2552
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
33
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 to be modified.
After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature
prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 are
saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, and MCR bits 5-7are set to a
logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5. Special character interrupts are cleared automatically after the next
received character.
T
ABLE
12: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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