參數(shù)資料
型號(hào)： XRT16L2552
廠商： Exar Corporation
英文描述： 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述： 2.25V至5.5V的杜阿爾特16字節(jié)FIFO
文件頁(yè)數(shù)： 11/47頁(yè)
文件大?。?/td> 413K
代理商： XRT16L2552
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
11
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in
Figure 6
.
The L2552 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides this 16X clock by
any divisor from 1 to 2
16
-1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5
shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
F
IGURE
6. O
PERATING
F
REQUENCY
C
HART
. R
EQUIRES
A
2K
OHMS
PULL
-
UP
RESIS
-
TOR
ON
XTAL2
PIN
TO
INCREASE
OPERATING
SPEED
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
T
ABLE
5: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
O
UTPUT
Data Rate
MCR Bit-7=0
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM P
ROGRAM
V
ALUE
(HEX)
DLL P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
48
30
00
30
0
38.4k
24
18
00
18
0
76.8k
12
0C
00
0C
0
60
50
40
30
3.0
4.5
5.5
3.5 4.0
5.0
Suppy Voltage
X
70
80
85
o
C
25
o
C
-40
o
C
Operating frequency for XR16L2552
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
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