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參數(shù)資料
| 型號： | XRT16L2552 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| 中文描述： | 2.25V至5.5V的杜阿爾特16字節(jié)FIFO |
| 文件頁數(shù)： | 27/47頁 |
| 文件大?。?/td> | 413K |
| 代理商： | XRT16L2552 |
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xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
27
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Table 10
shows the complete selections.
4.7
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
Line Control Register (LCR) - Read/Write
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
T
ABLE
10: R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCR
B
IT
-7
FCR
B
IT
-6
R
ECEIVE
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
1
1
0
1
0
1
1 (default)
4
8
14
Table-A. 16C550,
16C2550, 16C2552,
16C554, 16C580 com-
patible.
BIT-1
BIT-0
W
ORD
LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
BIT-2
W
ORD
LENGTH
S
TOP
BIT
LENGTH
(B
IT
TIME
(
S
))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
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