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參數(shù)資料
| 型號： | XRT16C854 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO |
| 中文描述： | 2.97V至5.5V四路UART的128字節(jié)FIFO |
| 文件頁數(shù)： | 28/54頁 |
| 文件大?。?/td> | 485K |
| 代理商： | XRT16C854 |
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XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
28
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table 10
).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon
character is received. ISR bit-5 indicates that CTS# or RTS# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive
FIFO
reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
T
ABLE
10: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
P
RIORITY
ISR R
EGISTER
S
TATUS
B
ITS
S
OURCE
OF
INTERRUPT
L
EVEL
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
0
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xoff or Special character)
7
1
0
0
0
0
0
CTS#, RTS# change of state
-
0
0
0
0
0
1
None (default)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT16L2552 | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XRT3591 | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591B | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591BID | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591BIP | SINGLECHIP V. 35 TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT16L2552 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XRT2588CN | 制造商:Exar Corporation 功能描述: |
| XR-T2713CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Subscriber Line Metering/Monitoring Circuit |
| XR-T3588 | 制造商:EXAR 制造商全稱:EXAR 功能描述:V.35 Interface Receiver/Transmitter |
| XR-T3588-89ES | 制造商:EXAR 制造商全稱:EXAR 功能描述:XR-T3588/89 Evaluation System |
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