- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376460 > XRT16C854 (Exar Corporation) 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO PDF資料下載
參數(shù)資料
| 型號： | XRT16C854 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO |
| 中文描述： | 2.97V至5.5V四路UART的128字節(jié)FIFO |
| 文件頁數(shù)： | 39/54頁 |
| 文件大?。?/td> | 485K |
| 代理商： | XRT16C854 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
xr
REV. 3.0.1
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
39
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level/hysteresis level. RTS# will return to a logic 0 when
FIFO data falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (logic 0)
before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow
control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.20
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
Table 7
.
4.21
FIFO Status Register (FSTAT) - Read/Write
This register is applicable only to the 100 pin QFP XR16C854. The FIFO Status Register provides a status
indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the
TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the
FSTAT register are placed on the data bus when the FSRS# pin (pin 76) is a logic 0. Also see FSRS# pin
description.
FSTAT[3:0]: TXRDY# A-D Status Bits
Please see
Table 5
for the interpretation of the TXRDY# signals.
FSTAT[7:4]: RXRDY# A-D Status Bits
Please see
Table 5
for the interpretation of the RXRDY# signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT16L2552 | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XRT3591 | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591B | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591BID | SINGLECHIP V. 35 TRANSCEIVER |
| XRT3591BIP | SINGLECHIP V. 35 TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT16L2552 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XRT2588CN | 制造商:Exar Corporation 功能描述: |
| XR-T2713CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Subscriber Line Metering/Monitoring Circuit |
| XR-T3588 | 制造商:EXAR 制造商全稱:EXAR 功能描述:V.35 Interface Receiver/Transmitter |
| XR-T3588-89ES | 制造商:EXAR 制造商全稱:EXAR 功能描述:XR-T3588/89 Evaluation System |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。