FIGURE 4. THE
參數(shù)資料
型號： XR17C152CM-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 5/62頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17C152 100TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
á
XR17C152
REV. 1.2.0
5V PCI BUS DUAL UART
13
.
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
TABLE 5: UART CHANNEL [1:0] INTERRUPT SOURCE ENCODING
PRIORITY
BIT[N+2]
BIT[N+1]
BIT[N]
INTERRUPT SOURCE(S)
x
000
None
1001
RXRDY and RX Line Status (logic OR of LSR[4:1])
2010
RXRDY Time-out
3011
TXRDY, THR or TSR (auto RS485 mode) empty
4100
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5101
Reserved.
6110
MPIO pin(s). Available only in channel 0, reserved in channel 1.
7111
TIMER Time-out. Available only in channel 0, reserved channel 1.
TABLE 6: UART CHANNEL [1:0] INTERRUPT CLEARING:
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
Rsvd
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Rsvd
Rsvd Ch-1 Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Rsvd
Rsvd Rsvd
Rsvd
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